99ceb03a1c
This formats all copyright comments according to SPDX formatting guidelines. Additionally, this resolves the remaining GPLv2 only licensed files by relicensing them to GPLv2.0-or-later.
415 lines
18 KiB
C++
415 lines
18 KiB
C++
// SPDX-FileCopyrightText: Copyright 2019 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include <array>
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#include <memory>
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#include <optional>
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#include <utility>
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#include "common/assert.h"
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#include "common/common_types.h"
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#include "common/div_ceil.h"
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#include "video_core/host_shaders/astc_decoder_comp_spv.h"
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#include "video_core/host_shaders/vulkan_quad_indexed_comp_spv.h"
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#include "video_core/host_shaders/vulkan_uint8_comp_spv.h"
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#include "video_core/renderer_vulkan/vk_compute_pass.h"
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#include "video_core/renderer_vulkan/vk_descriptor_pool.h"
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#include "video_core/renderer_vulkan/vk_scheduler.h"
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#include "video_core/renderer_vulkan/vk_staging_buffer_pool.h"
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#include "video_core/renderer_vulkan/vk_texture_cache.h"
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#include "video_core/renderer_vulkan/vk_update_descriptor.h"
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#include "video_core/texture_cache/accelerated_swizzle.h"
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#include "video_core/texture_cache/types.h"
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#include "video_core/textures/decoders.h"
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#include "video_core/vulkan_common/vulkan_device.h"
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#include "video_core/vulkan_common/vulkan_wrapper.h"
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namespace Vulkan {
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using Tegra::Texture::SWIZZLE_TABLE;
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namespace {
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constexpr u32 ASTC_BINDING_INPUT_BUFFER = 0;
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constexpr u32 ASTC_BINDING_OUTPUT_IMAGE = 1;
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constexpr size_t ASTC_NUM_BINDINGS = 2;
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template <size_t size>
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inline constexpr VkPushConstantRange COMPUTE_PUSH_CONSTANT_RANGE{
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.offset = 0,
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.size = static_cast<u32>(size),
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};
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constexpr std::array<VkDescriptorSetLayoutBinding, 2> INPUT_OUTPUT_DESCRIPTOR_SET_BINDINGS{{
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{
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.binding = 0,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = nullptr,
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},
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{
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.binding = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = nullptr,
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},
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}};
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constexpr DescriptorBankInfo INPUT_OUTPUT_BANK_INFO{
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.uniform_buffers = 0,
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.storage_buffers = 2,
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.texture_buffers = 0,
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.image_buffers = 0,
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.textures = 0,
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.images = 0,
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.score = 2,
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};
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constexpr std::array<VkDescriptorSetLayoutBinding, ASTC_NUM_BINDINGS> ASTC_DESCRIPTOR_SET_BINDINGS{{
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{
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.binding = ASTC_BINDING_INPUT_BUFFER,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = nullptr,
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},
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{
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.binding = ASTC_BINDING_OUTPUT_IMAGE,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = nullptr,
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},
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}};
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constexpr DescriptorBankInfo ASTC_BANK_INFO{
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.uniform_buffers = 0,
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.storage_buffers = 1,
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.texture_buffers = 0,
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.image_buffers = 0,
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.textures = 0,
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.images = 1,
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.score = 2,
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};
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constexpr VkDescriptorUpdateTemplateEntryKHR INPUT_OUTPUT_DESCRIPTOR_UPDATE_TEMPLATE{
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.dstBinding = 0,
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.dstArrayElement = 0,
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.descriptorCount = 2,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
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.offset = 0,
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.stride = sizeof(DescriptorUpdateEntry),
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};
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constexpr std::array<VkDescriptorUpdateTemplateEntryKHR, ASTC_NUM_BINDINGS>
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ASTC_PASS_DESCRIPTOR_UPDATE_TEMPLATE_ENTRY{{
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{
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.dstBinding = ASTC_BINDING_INPUT_BUFFER,
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.dstArrayElement = 0,
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.descriptorCount = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
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.offset = ASTC_BINDING_INPUT_BUFFER * sizeof(DescriptorUpdateEntry),
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.stride = sizeof(DescriptorUpdateEntry),
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},
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{
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.dstBinding = ASTC_BINDING_OUTPUT_IMAGE,
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.dstArrayElement = 0,
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.descriptorCount = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
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.offset = ASTC_BINDING_OUTPUT_IMAGE * sizeof(DescriptorUpdateEntry),
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.stride = sizeof(DescriptorUpdateEntry),
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},
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}};
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struct AstcPushConstants {
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std::array<u32, 2> blocks_dims;
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u32 layer_stride;
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u32 block_size;
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u32 x_shift;
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u32 block_height;
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u32 block_height_mask;
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};
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} // Anonymous namespace
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ComputePass::ComputePass(const Device& device_, DescriptorPool& descriptor_pool,
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vk::Span<VkDescriptorSetLayoutBinding> bindings,
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vk::Span<VkDescriptorUpdateTemplateEntryKHR> templates,
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const DescriptorBankInfo& bank_info,
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vk::Span<VkPushConstantRange> push_constants, std::span<const u32> code)
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: device{device_} {
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descriptor_set_layout = device.GetLogical().CreateDescriptorSetLayout({
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.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
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.pNext = nullptr,
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.flags = 0,
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.bindingCount = bindings.size(),
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.pBindings = bindings.data(),
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});
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layout = device.GetLogical().CreatePipelineLayout({
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.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
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.pNext = nullptr,
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.flags = 0,
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.setLayoutCount = 1,
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.pSetLayouts = descriptor_set_layout.address(),
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.pushConstantRangeCount = push_constants.size(),
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.pPushConstantRanges = push_constants.data(),
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});
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if (!templates.empty()) {
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descriptor_template = device.GetLogical().CreateDescriptorUpdateTemplateKHR({
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.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_UPDATE_TEMPLATE_CREATE_INFO_KHR,
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.pNext = nullptr,
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.flags = 0,
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.descriptorUpdateEntryCount = templates.size(),
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.pDescriptorUpdateEntries = templates.data(),
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.templateType = VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR,
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.descriptorSetLayout = *descriptor_set_layout,
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.pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
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.pipelineLayout = *layout,
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.set = 0,
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});
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descriptor_allocator = descriptor_pool.Allocator(*descriptor_set_layout, bank_info);
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}
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module = device.GetLogical().CreateShaderModule({
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.sType = VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO,
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.pNext = nullptr,
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.flags = 0,
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.codeSize = static_cast<u32>(code.size_bytes()),
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.pCode = code.data(),
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});
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device.SaveShader(code);
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pipeline = device.GetLogical().CreateComputePipeline({
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.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
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.pNext = nullptr,
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.flags = 0,
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.stage{
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.pNext = nullptr,
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.flags = 0,
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.stage = VK_SHADER_STAGE_COMPUTE_BIT,
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.module = *module,
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.pName = "main",
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.pSpecializationInfo = nullptr,
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},
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.layout = *layout,
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.basePipelineHandle = nullptr,
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.basePipelineIndex = 0,
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});
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}
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ComputePass::~ComputePass() = default;
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Uint8Pass::Uint8Pass(const Device& device_, VKScheduler& scheduler_,
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DescriptorPool& descriptor_pool, StagingBufferPool& staging_buffer_pool_,
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VKUpdateDescriptorQueue& update_descriptor_queue_)
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: ComputePass(device_, descriptor_pool, INPUT_OUTPUT_DESCRIPTOR_SET_BINDINGS,
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INPUT_OUTPUT_DESCRIPTOR_UPDATE_TEMPLATE, INPUT_OUTPUT_BANK_INFO, {},
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VULKAN_UINT8_COMP_SPV),
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scheduler{scheduler_}, staging_buffer_pool{staging_buffer_pool_},
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update_descriptor_queue{update_descriptor_queue_} {}
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Uint8Pass::~Uint8Pass() = default;
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std::pair<VkBuffer, VkDeviceSize> Uint8Pass::Assemble(u32 num_vertices, VkBuffer src_buffer,
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u32 src_offset) {
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const u32 staging_size = static_cast<u32>(num_vertices * sizeof(u16));
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const auto staging = staging_buffer_pool.Request(staging_size, MemoryUsage::DeviceLocal);
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update_descriptor_queue.Acquire();
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update_descriptor_queue.AddBuffer(src_buffer, src_offset, num_vertices);
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update_descriptor_queue.AddBuffer(staging.buffer, staging.offset, staging_size);
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const void* const descriptor_data{update_descriptor_queue.UpdateData()};
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scheduler.RequestOutsideRenderPassOperationContext();
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scheduler.Record([this, descriptor_data, num_vertices](vk::CommandBuffer cmdbuf) {
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static constexpr u32 DISPATCH_SIZE = 1024;
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static constexpr VkMemoryBarrier WRITE_BARRIER{
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.sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER,
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.pNext = nullptr,
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.srcAccessMask = VK_ACCESS_SHADER_WRITE_BIT,
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.dstAccessMask = VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT,
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};
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const VkDescriptorSet set = descriptor_allocator.Commit();
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device.GetLogical().UpdateDescriptorSet(set, *descriptor_template, descriptor_data);
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cmdbuf.BindPipeline(VK_PIPELINE_BIND_POINT_COMPUTE, *pipeline);
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cmdbuf.BindDescriptorSets(VK_PIPELINE_BIND_POINT_COMPUTE, *layout, 0, set, {});
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cmdbuf.Dispatch(Common::DivCeil(num_vertices, DISPATCH_SIZE), 1, 1);
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cmdbuf.PipelineBarrier(VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
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VK_PIPELINE_STAGE_VERTEX_INPUT_BIT, 0, WRITE_BARRIER);
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});
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return {staging.buffer, staging.offset};
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}
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QuadIndexedPass::QuadIndexedPass(const Device& device_, VKScheduler& scheduler_,
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DescriptorPool& descriptor_pool_,
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StagingBufferPool& staging_buffer_pool_,
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VKUpdateDescriptorQueue& update_descriptor_queue_)
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: ComputePass(device_, descriptor_pool_, INPUT_OUTPUT_DESCRIPTOR_SET_BINDINGS,
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INPUT_OUTPUT_DESCRIPTOR_UPDATE_TEMPLATE, INPUT_OUTPUT_BANK_INFO,
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COMPUTE_PUSH_CONSTANT_RANGE<sizeof(u32) * 2>, VULKAN_QUAD_INDEXED_COMP_SPV),
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scheduler{scheduler_}, staging_buffer_pool{staging_buffer_pool_},
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update_descriptor_queue{update_descriptor_queue_} {}
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QuadIndexedPass::~QuadIndexedPass() = default;
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std::pair<VkBuffer, VkDeviceSize> QuadIndexedPass::Assemble(
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Tegra::Engines::Maxwell3D::Regs::IndexFormat index_format, u32 num_vertices, u32 base_vertex,
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VkBuffer src_buffer, u32 src_offset) {
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const u32 index_shift = [index_format] {
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switch (index_format) {
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case Tegra::Engines::Maxwell3D::Regs::IndexFormat::UnsignedByte:
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return 0;
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case Tegra::Engines::Maxwell3D::Regs::IndexFormat::UnsignedShort:
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return 1;
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case Tegra::Engines::Maxwell3D::Regs::IndexFormat::UnsignedInt:
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return 2;
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}
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UNREACHABLE();
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return 2;
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}();
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const u32 input_size = num_vertices << index_shift;
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const u32 num_tri_vertices = (num_vertices / 4) * 6;
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const std::size_t staging_size = num_tri_vertices * sizeof(u32);
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const auto staging = staging_buffer_pool.Request(staging_size, MemoryUsage::DeviceLocal);
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update_descriptor_queue.Acquire();
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update_descriptor_queue.AddBuffer(src_buffer, src_offset, input_size);
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update_descriptor_queue.AddBuffer(staging.buffer, staging.offset, staging_size);
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const void* const descriptor_data{update_descriptor_queue.UpdateData()};
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scheduler.RequestOutsideRenderPassOperationContext();
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scheduler.Record([this, descriptor_data, num_tri_vertices, base_vertex,
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index_shift](vk::CommandBuffer cmdbuf) {
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static constexpr u32 DISPATCH_SIZE = 1024;
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static constexpr VkMemoryBarrier WRITE_BARRIER{
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.sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER,
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.pNext = nullptr,
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.srcAccessMask = VK_ACCESS_SHADER_WRITE_BIT,
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.dstAccessMask = VK_ACCESS_INDEX_READ_BIT,
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};
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const std::array<u32, 2> push_constants{base_vertex, index_shift};
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const VkDescriptorSet set = descriptor_allocator.Commit();
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device.GetLogical().UpdateDescriptorSet(set, *descriptor_template, descriptor_data);
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cmdbuf.BindPipeline(VK_PIPELINE_BIND_POINT_COMPUTE, *pipeline);
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cmdbuf.BindDescriptorSets(VK_PIPELINE_BIND_POINT_COMPUTE, *layout, 0, set, {});
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cmdbuf.PushConstants(*layout, VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(push_constants),
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&push_constants);
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cmdbuf.Dispatch(Common::DivCeil(num_tri_vertices, DISPATCH_SIZE), 1, 1);
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cmdbuf.PipelineBarrier(VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
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VK_PIPELINE_STAGE_VERTEX_INPUT_BIT, 0, WRITE_BARRIER);
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});
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return {staging.buffer, staging.offset};
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}
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ASTCDecoderPass::ASTCDecoderPass(const Device& device_, VKScheduler& scheduler_,
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DescriptorPool& descriptor_pool_,
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StagingBufferPool& staging_buffer_pool_,
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VKUpdateDescriptorQueue& update_descriptor_queue_,
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MemoryAllocator& memory_allocator_)
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: ComputePass(device_, descriptor_pool_, ASTC_DESCRIPTOR_SET_BINDINGS,
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ASTC_PASS_DESCRIPTOR_UPDATE_TEMPLATE_ENTRY, ASTC_BANK_INFO,
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COMPUTE_PUSH_CONSTANT_RANGE<sizeof(AstcPushConstants)>, ASTC_DECODER_COMP_SPV),
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scheduler{scheduler_}, staging_buffer_pool{staging_buffer_pool_},
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update_descriptor_queue{update_descriptor_queue_}, memory_allocator{memory_allocator_} {}
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ASTCDecoderPass::~ASTCDecoderPass() = default;
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void ASTCDecoderPass::Assemble(Image& image, const StagingBufferRef& map,
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std::span<const VideoCommon::SwizzleParameters> swizzles) {
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using namespace VideoCommon::Accelerated;
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const std::array<u32, 2> block_dims{
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VideoCore::Surface::DefaultBlockWidth(image.info.format),
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VideoCore::Surface::DefaultBlockHeight(image.info.format),
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};
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scheduler.RequestOutsideRenderPassOperationContext();
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const VkPipeline vk_pipeline = *pipeline;
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const VkImageAspectFlags aspect_mask = image.AspectMask();
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const VkImage vk_image = image.Handle();
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const bool is_initialized = image.ExchangeInitialization();
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scheduler.Record(
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[vk_pipeline, vk_image, aspect_mask, is_initialized](vk::CommandBuffer cmdbuf) {
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const VkImageMemoryBarrier image_barrier{
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.sType = VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER,
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.pNext = nullptr,
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.srcAccessMask = is_initialized ? VK_ACCESS_SHADER_WRITE_BIT : VkAccessFlags{},
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.dstAccessMask = VK_ACCESS_SHADER_READ_BIT | VK_ACCESS_SHADER_WRITE_BIT,
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.oldLayout = is_initialized ? VK_IMAGE_LAYOUT_GENERAL : VK_IMAGE_LAYOUT_UNDEFINED,
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.newLayout = VK_IMAGE_LAYOUT_GENERAL,
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.srcQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED,
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.dstQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED,
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.image = vk_image,
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.subresourceRange{
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.aspectMask = aspect_mask,
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.baseMipLevel = 0,
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.levelCount = VK_REMAINING_MIP_LEVELS,
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.baseArrayLayer = 0,
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.layerCount = VK_REMAINING_ARRAY_LAYERS,
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},
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};
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cmdbuf.PipelineBarrier(is_initialized ? VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
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: VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
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VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT, 0, image_barrier);
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cmdbuf.BindPipeline(VK_PIPELINE_BIND_POINT_COMPUTE, vk_pipeline);
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});
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for (const VideoCommon::SwizzleParameters& swizzle : swizzles) {
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const size_t input_offset = swizzle.buffer_offset + map.offset;
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const u32 num_dispatches_x = Common::DivCeil(swizzle.num_tiles.width, 8U);
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const u32 num_dispatches_y = Common::DivCeil(swizzle.num_tiles.height, 8U);
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const u32 num_dispatches_z = image.info.resources.layers;
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update_descriptor_queue.Acquire();
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update_descriptor_queue.AddBuffer(map.buffer, input_offset,
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image.guest_size_bytes - swizzle.buffer_offset);
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update_descriptor_queue.AddImage(image.StorageImageView(swizzle.level));
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const void* const descriptor_data{update_descriptor_queue.UpdateData()};
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// To unswizzle the ASTC data
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const auto params = MakeBlockLinearSwizzle2DParams(swizzle, image.info);
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ASSERT(params.origin == (std::array<u32, 3>{0, 0, 0}));
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ASSERT(params.destination == (std::array<s32, 3>{0, 0, 0}));
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ASSERT(params.bytes_per_block_log2 == 4);
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scheduler.Record([this, num_dispatches_x, num_dispatches_y, num_dispatches_z, block_dims,
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params, descriptor_data](vk::CommandBuffer cmdbuf) {
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const AstcPushConstants uniforms{
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.blocks_dims = block_dims,
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.layer_stride = params.layer_stride,
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.block_size = params.block_size,
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.x_shift = params.x_shift,
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.block_height = params.block_height,
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.block_height_mask = params.block_height_mask,
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};
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const VkDescriptorSet set = descriptor_allocator.Commit();
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device.GetLogical().UpdateDescriptorSet(set, *descriptor_template, descriptor_data);
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cmdbuf.BindDescriptorSets(VK_PIPELINE_BIND_POINT_COMPUTE, *layout, 0, set, {});
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cmdbuf.PushConstants(*layout, VK_SHADER_STAGE_COMPUTE_BIT, uniforms);
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cmdbuf.Dispatch(num_dispatches_x, num_dispatches_y, num_dispatches_z);
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});
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}
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scheduler.Record([vk_image, aspect_mask](vk::CommandBuffer cmdbuf) {
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const VkImageMemoryBarrier image_barrier{
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.sType = VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER,
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.pNext = nullptr,
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.srcAccessMask = VK_ACCESS_SHADER_WRITE_BIT,
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.dstAccessMask = VK_ACCESS_SHADER_READ_BIT | VK_ACCESS_SHADER_WRITE_BIT,
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.oldLayout = VK_IMAGE_LAYOUT_GENERAL,
|
|
.newLayout = VK_IMAGE_LAYOUT_GENERAL,
|
|
.srcQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED,
|
|
.dstQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED,
|
|
.image = vk_image,
|
|
.subresourceRange{
|
|
.aspectMask = aspect_mask,
|
|
.baseMipLevel = 0,
|
|
.levelCount = VK_REMAINING_MIP_LEVELS,
|
|
.baseArrayLayer = 0,
|
|
.layerCount = VK_REMAINING_ARRAY_LAYERS,
|
|
},
|
|
};
|
|
cmdbuf.PipelineBarrier(VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
|
|
VK_PIPELINE_STAGE_ALL_COMMANDS_BIT, 0, image_barrier);
|
|
});
|
|
scheduler.Finish();
|
|
}
|
|
|
|
} // namespace Vulkan
|