e996f1ad09
Fix a bug where the memory allocator could leave gaps between commits. To fix this the allocation algorithm was reworked, although it's still short in number of lines of code. Rework the allocation API to self-contained movable objects instead of naively using an unique_ptr to do the job for us. Remove the VK prefix.
323 lines
14 KiB
C++
323 lines
14 KiB
C++
// Copyright 2019 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <cstring>
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#include <memory>
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#include <optional>
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#include <utility>
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#include "common/alignment.h"
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#include "common/assert.h"
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#include "common/common_types.h"
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#include "video_core/host_shaders/vulkan_quad_array_comp_spv.h"
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#include "video_core/host_shaders/vulkan_quad_indexed_comp_spv.h"
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#include "video_core/host_shaders/vulkan_uint8_comp_spv.h"
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#include "video_core/renderer_vulkan/vk_compute_pass.h"
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#include "video_core/renderer_vulkan/vk_descriptor_pool.h"
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#include "video_core/renderer_vulkan/vk_scheduler.h"
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#include "video_core/renderer_vulkan/vk_staging_buffer_pool.h"
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#include "video_core/renderer_vulkan/vk_update_descriptor.h"
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#include "video_core/vulkan_common/vulkan_device.h"
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#include "video_core/vulkan_common/vulkan_wrapper.h"
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namespace Vulkan {
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namespace {
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VkDescriptorSetLayoutBinding BuildQuadArrayPassDescriptorSetLayoutBinding() {
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return {
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.binding = 0,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = nullptr,
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};
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}
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VkDescriptorUpdateTemplateEntryKHR BuildQuadArrayPassDescriptorUpdateTemplateEntry() {
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return {
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.dstBinding = 0,
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.dstArrayElement = 0,
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.descriptorCount = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
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.offset = 0,
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.stride = sizeof(DescriptorUpdateEntry),
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};
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}
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VkPushConstantRange BuildComputePushConstantRange(std::size_t size) {
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return {
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.offset = 0,
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.size = static_cast<u32>(size),
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};
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}
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std::array<VkDescriptorSetLayoutBinding, 2> BuildInputOutputDescriptorSetBindings() {
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return {{
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{
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.binding = 0,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = nullptr,
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},
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{
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.binding = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = nullptr,
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},
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}};
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}
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VkDescriptorUpdateTemplateEntryKHR BuildInputOutputDescriptorUpdateTemplate() {
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return {
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.dstBinding = 0,
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.dstArrayElement = 0,
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.descriptorCount = 2,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
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.offset = 0,
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.stride = sizeof(DescriptorUpdateEntry),
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};
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}
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} // Anonymous namespace
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VKComputePass::VKComputePass(const Device& device, VKDescriptorPool& descriptor_pool,
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vk::Span<VkDescriptorSetLayoutBinding> bindings,
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vk::Span<VkDescriptorUpdateTemplateEntryKHR> templates,
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vk::Span<VkPushConstantRange> push_constants,
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std::span<const u32> code) {
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descriptor_set_layout = device.GetLogical().CreateDescriptorSetLayout({
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.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
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.pNext = nullptr,
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.flags = 0,
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.bindingCount = bindings.size(),
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.pBindings = bindings.data(),
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});
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layout = device.GetLogical().CreatePipelineLayout({
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.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
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.pNext = nullptr,
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.flags = 0,
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.setLayoutCount = 1,
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.pSetLayouts = descriptor_set_layout.address(),
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.pushConstantRangeCount = push_constants.size(),
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.pPushConstantRanges = push_constants.data(),
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});
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if (!templates.empty()) {
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descriptor_template = device.GetLogical().CreateDescriptorUpdateTemplateKHR({
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.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_UPDATE_TEMPLATE_CREATE_INFO_KHR,
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.pNext = nullptr,
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.flags = 0,
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.descriptorUpdateEntryCount = templates.size(),
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.pDescriptorUpdateEntries = templates.data(),
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.templateType = VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR,
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.descriptorSetLayout = *descriptor_set_layout,
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.pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
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.pipelineLayout = *layout,
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.set = 0,
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});
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descriptor_allocator.emplace(descriptor_pool, *descriptor_set_layout);
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}
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module = device.GetLogical().CreateShaderModule({
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.sType = VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO,
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.pNext = nullptr,
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.flags = 0,
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.codeSize = static_cast<u32>(code.size_bytes()),
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.pCode = code.data(),
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});
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pipeline = device.GetLogical().CreateComputePipeline({
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.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
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.pNext = nullptr,
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.flags = 0,
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.stage =
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{
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.pNext = nullptr,
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.flags = 0,
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.stage = VK_SHADER_STAGE_COMPUTE_BIT,
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.module = *module,
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.pName = "main",
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.pSpecializationInfo = nullptr,
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},
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.layout = *layout,
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.basePipelineHandle = nullptr,
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.basePipelineIndex = 0,
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});
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}
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VKComputePass::~VKComputePass() = default;
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VkDescriptorSet VKComputePass::CommitDescriptorSet(
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VKUpdateDescriptorQueue& update_descriptor_queue) {
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if (!descriptor_template) {
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return nullptr;
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}
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const VkDescriptorSet set = descriptor_allocator->Commit();
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update_descriptor_queue.Send(*descriptor_template, set);
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return set;
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}
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QuadArrayPass::QuadArrayPass(const Device& device_, VKScheduler& scheduler_,
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VKDescriptorPool& descriptor_pool_,
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StagingBufferPool& staging_buffer_pool_,
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VKUpdateDescriptorQueue& update_descriptor_queue_)
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: VKComputePass(device_, descriptor_pool_, BuildQuadArrayPassDescriptorSetLayoutBinding(),
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BuildQuadArrayPassDescriptorUpdateTemplateEntry(),
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BuildComputePushConstantRange(sizeof(u32)), VULKAN_QUAD_ARRAY_COMP_SPV),
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scheduler{scheduler_}, staging_buffer_pool{staging_buffer_pool_},
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update_descriptor_queue{update_descriptor_queue_} {}
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QuadArrayPass::~QuadArrayPass() = default;
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std::pair<VkBuffer, VkDeviceSize> QuadArrayPass::Assemble(u32 num_vertices, u32 first) {
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const u32 num_triangle_vertices = (num_vertices / 4) * 6;
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const std::size_t staging_size = num_triangle_vertices * sizeof(u32);
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const auto staging_ref = staging_buffer_pool.Request(staging_size, false);
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update_descriptor_queue.Acquire();
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update_descriptor_queue.AddBuffer(staging_ref.buffer, 0, staging_size);
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const VkDescriptorSet set = CommitDescriptorSet(update_descriptor_queue);
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scheduler.RequestOutsideRenderPassOperationContext();
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ASSERT(num_vertices % 4 == 0);
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const u32 num_quads = num_vertices / 4;
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scheduler.Record([layout = *layout, pipeline = *pipeline, buffer = staging_ref.buffer,
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num_quads, first, set](vk::CommandBuffer cmdbuf) {
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constexpr u32 dispatch_size = 1024;
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cmdbuf.BindPipeline(VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
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cmdbuf.BindDescriptorSets(VK_PIPELINE_BIND_POINT_COMPUTE, layout, 0, set, {});
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cmdbuf.PushConstants(layout, VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(first), &first);
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cmdbuf.Dispatch(Common::AlignUp(num_quads, dispatch_size) / dispatch_size, 1, 1);
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VkBufferMemoryBarrier barrier;
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barrier.sType = VK_STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER;
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barrier.pNext = nullptr;
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barrier.srcAccessMask = VK_ACCESS_SHADER_WRITE_BIT;
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barrier.dstAccessMask = VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT;
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barrier.srcQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED;
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barrier.dstQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED;
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barrier.buffer = buffer;
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barrier.offset = 0;
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barrier.size = static_cast<VkDeviceSize>(num_quads) * 6 * sizeof(u32);
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cmdbuf.PipelineBarrier(VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
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VK_PIPELINE_STAGE_VERTEX_INPUT_BIT, 0, {}, {barrier}, {});
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});
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return {staging_ref.buffer, 0};
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}
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Uint8Pass::Uint8Pass(const Device& device, VKScheduler& scheduler_,
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VKDescriptorPool& descriptor_pool, StagingBufferPool& staging_buffer_pool_,
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VKUpdateDescriptorQueue& update_descriptor_queue_)
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: VKComputePass(device, descriptor_pool, BuildInputOutputDescriptorSetBindings(),
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BuildInputOutputDescriptorUpdateTemplate(), {}, VULKAN_UINT8_COMP_SPV),
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scheduler{scheduler_}, staging_buffer_pool{staging_buffer_pool_},
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update_descriptor_queue{update_descriptor_queue_} {}
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Uint8Pass::~Uint8Pass() = default;
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std::pair<VkBuffer, u64> Uint8Pass::Assemble(u32 num_vertices, VkBuffer src_buffer,
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u64 src_offset) {
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const u32 staging_size = static_cast<u32>(num_vertices * sizeof(u16));
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const auto staging_ref = staging_buffer_pool.Request(staging_size, false);
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update_descriptor_queue.Acquire();
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update_descriptor_queue.AddBuffer(src_buffer, src_offset, num_vertices);
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update_descriptor_queue.AddBuffer(staging_ref.buffer, 0, staging_size);
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const VkDescriptorSet set = CommitDescriptorSet(update_descriptor_queue);
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scheduler.RequestOutsideRenderPassOperationContext();
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scheduler.Record([layout = *layout, pipeline = *pipeline, buffer = staging_ref.buffer, set,
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num_vertices](vk::CommandBuffer cmdbuf) {
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constexpr u32 dispatch_size = 1024;
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cmdbuf.BindPipeline(VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
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cmdbuf.BindDescriptorSets(VK_PIPELINE_BIND_POINT_COMPUTE, layout, 0, set, {});
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cmdbuf.Dispatch(Common::AlignUp(num_vertices, dispatch_size) / dispatch_size, 1, 1);
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VkBufferMemoryBarrier barrier;
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barrier.sType = VK_STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER;
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barrier.pNext = nullptr;
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barrier.srcAccessMask = VK_ACCESS_SHADER_WRITE_BIT;
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barrier.dstAccessMask = VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT;
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barrier.srcQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED;
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barrier.dstQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED;
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barrier.buffer = buffer;
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barrier.offset = 0;
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barrier.size = static_cast<VkDeviceSize>(num_vertices * sizeof(u16));
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cmdbuf.PipelineBarrier(VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
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VK_PIPELINE_STAGE_VERTEX_INPUT_BIT, 0, {}, barrier, {});
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});
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return {staging_ref.buffer, 0};
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}
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QuadIndexedPass::QuadIndexedPass(const Device& device_, VKScheduler& scheduler_,
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VKDescriptorPool& descriptor_pool_,
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StagingBufferPool& staging_buffer_pool_,
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VKUpdateDescriptorQueue& update_descriptor_queue_)
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: VKComputePass(device_, descriptor_pool_, BuildInputOutputDescriptorSetBindings(),
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BuildInputOutputDescriptorUpdateTemplate(),
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BuildComputePushConstantRange(sizeof(u32) * 2), VULKAN_QUAD_INDEXED_COMP_SPV),
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scheduler{scheduler_}, staging_buffer_pool{staging_buffer_pool_},
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update_descriptor_queue{update_descriptor_queue_} {}
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QuadIndexedPass::~QuadIndexedPass() = default;
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std::pair<VkBuffer, u64> QuadIndexedPass::Assemble(
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Tegra::Engines::Maxwell3D::Regs::IndexFormat index_format, u32 num_vertices, u32 base_vertex,
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VkBuffer src_buffer, u64 src_offset) {
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const u32 index_shift = [index_format] {
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switch (index_format) {
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case Tegra::Engines::Maxwell3D::Regs::IndexFormat::UnsignedByte:
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return 0;
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case Tegra::Engines::Maxwell3D::Regs::IndexFormat::UnsignedShort:
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return 1;
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case Tegra::Engines::Maxwell3D::Regs::IndexFormat::UnsignedInt:
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return 2;
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}
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UNREACHABLE();
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return 2;
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}();
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const u32 input_size = num_vertices << index_shift;
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const u32 num_tri_vertices = (num_vertices / 4) * 6;
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const std::size_t staging_size = num_tri_vertices * sizeof(u32);
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const auto staging_ref = staging_buffer_pool.Request(staging_size, false);
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update_descriptor_queue.Acquire();
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update_descriptor_queue.AddBuffer(src_buffer, src_offset, input_size);
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update_descriptor_queue.AddBuffer(staging_ref.buffer, 0, staging_size);
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const VkDescriptorSet set = CommitDescriptorSet(update_descriptor_queue);
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scheduler.RequestOutsideRenderPassOperationContext();
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scheduler.Record([layout = *layout, pipeline = *pipeline, buffer = staging_ref.buffer, set,
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num_tri_vertices, base_vertex, index_shift](vk::CommandBuffer cmdbuf) {
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static constexpr u32 dispatch_size = 1024;
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const std::array push_constants = {base_vertex, index_shift};
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cmdbuf.BindPipeline(VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
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cmdbuf.BindDescriptorSets(VK_PIPELINE_BIND_POINT_COMPUTE, layout, 0, set, {});
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cmdbuf.PushConstants(layout, VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(push_constants),
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&push_constants);
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cmdbuf.Dispatch(Common::AlignUp(num_tri_vertices, dispatch_size) / dispatch_size, 1, 1);
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VkBufferMemoryBarrier barrier;
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barrier.sType = VK_STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER;
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barrier.pNext = nullptr;
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barrier.srcAccessMask = VK_ACCESS_SHADER_WRITE_BIT;
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barrier.dstAccessMask = VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT;
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barrier.srcQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED;
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barrier.dstQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED;
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barrier.buffer = buffer;
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barrier.offset = 0;
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barrier.size = static_cast<VkDeviceSize>(num_tri_vertices * sizeof(u32));
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cmdbuf.PipelineBarrier(VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
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VK_PIPELINE_STAGE_VERTEX_INPUT_BIT, 0, {}, barrier, {});
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});
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return {staging_ref.buffer, 0};
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}
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} // namespace Vulkan
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