f00641459e
There were two issues with block linear copies. First the swizzling was wrong and this commit reimplements them. The other issue was that these copies are generally used to download render targets from the GPU and yuzu was not downloading them from host GPU memory unless the extreme GPU accuracy setting was selected. This commit enables cached memory reads for all accuracy levels. - Fixes level thumbnails in Super Mario Maker 2.
216 lines
8.9 KiB
C++
216 lines
8.9 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/assert.h"
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#include "common/logging/log.h"
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#include "core/core.h"
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#include "core/settings.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/engines/maxwell_dma.h"
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#include "video_core/memory_manager.h"
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#include "video_core/renderer_base.h"
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#include "video_core/textures/decoders.h"
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namespace Tegra::Engines {
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using namespace Texture;
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MaxwellDMA::MaxwellDMA(Core::System& system, MemoryManager& memory_manager)
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: system{system}, memory_manager{memory_manager} {}
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void MaxwellDMA::CallMethod(u32 method, u32 method_argument, bool is_last_call) {
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ASSERT_MSG(method < NUM_REGS, "Invalid MaxwellDMA register");
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regs.reg_array[method] = method_argument;
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if (method == offsetof(Regs, launch_dma) / sizeof(u32)) {
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Launch();
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}
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}
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void MaxwellDMA::CallMultiMethod(u32 method, const u32* base_start, u32 amount,
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u32 methods_pending) {
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for (size_t i = 0; i < amount; ++i) {
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CallMethod(method, base_start[i], methods_pending - static_cast<u32>(i) <= 1);
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}
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}
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void MaxwellDMA::Launch() {
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LOG_TRACE(Render_OpenGL, "DMA copy 0x{:x} -> 0x{:x}", static_cast<GPUVAddr>(regs.offset_in),
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static_cast<GPUVAddr>(regs.offset_out));
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// TODO(Subv): Perform more research and implement all features of this engine.
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const LaunchDMA& launch = regs.launch_dma;
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ASSERT(launch.remap_enable == 0);
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ASSERT(launch.semaphore_type == LaunchDMA::SemaphoreType::NONE);
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ASSERT(launch.interrupt_type == LaunchDMA::InterruptType::NONE);
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ASSERT(launch.data_transfer_type == LaunchDMA::DataTransferType::NON_PIPELINED);
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ASSERT(regs.dst_params.origin.x == 0);
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ASSERT(regs.dst_params.origin.y == 0);
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const bool is_src_pitch = launch.src_memory_layout == LaunchDMA::MemoryLayout::PITCH;
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const bool is_dst_pitch = launch.dst_memory_layout == LaunchDMA::MemoryLayout::PITCH;
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if (!is_src_pitch && !is_dst_pitch) {
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// If both the source and the destination are in block layout, assert.
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UNREACHABLE_MSG("Tiled->Tiled DMA transfers are not yet implemented");
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return;
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}
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// All copies here update the main memory, so mark all rasterizer states as invalid.
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system.GPU().Maxwell3D().OnMemoryWrite();
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if (is_src_pitch && is_dst_pitch) {
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CopyPitchToPitch();
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} else {
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ASSERT(launch.multi_line_enable == 1);
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if (!is_src_pitch && is_dst_pitch) {
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CopyBlockLinearToPitch();
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} else {
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CopyPitchToBlockLinear();
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}
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}
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}
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void MaxwellDMA::CopyPitchToPitch() {
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// When `multi_line_enable` bit is disabled the copy is performed as if we were copying a 1D
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// buffer of length `line_length_in`.
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// Otherwise we copy a 2D image of dimensions (line_length_in, line_count).
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if (!regs.launch_dma.multi_line_enable) {
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memory_manager.CopyBlock(regs.offset_out, regs.offset_in, regs.line_length_in);
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return;
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}
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// Perform a line-by-line copy.
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// We're going to take a subrect of size (line_length_in, line_count) from the source rectangle.
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// There is no need to manually flush/invalidate the regions because CopyBlock does that for us.
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for (u32 line = 0; line < regs.line_count; ++line) {
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const GPUVAddr source_line = regs.offset_in + static_cast<size_t>(line) * regs.pitch_in;
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const GPUVAddr dest_line = regs.offset_out + static_cast<size_t>(line) * regs.pitch_out;
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memory_manager.CopyBlock(dest_line, source_line, regs.line_length_in);
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}
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}
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void MaxwellDMA::CopyBlockLinearToPitch() {
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UNIMPLEMENTED_IF(regs.src_params.block_size.depth != 0);
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UNIMPLEMENTED_IF(regs.src_params.layer != 0);
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// Optimized path for micro copies.
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const size_t dst_size = static_cast<size_t>(regs.pitch_out) * regs.line_count;
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if (dst_size < GOB_SIZE && regs.pitch_out <= GOB_SIZE_X) {
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FastCopyBlockLinearToPitch();
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return;
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}
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// Deswizzle the input and copy it over.
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const u32 bytes_per_pixel = regs.pitch_out / regs.line_length_in;
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const Parameters& src_params = regs.src_params;
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const u32 width = src_params.width;
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const u32 height = src_params.height;
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const u32 depth = src_params.depth;
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const u32 block_height = src_params.block_size.height;
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const u32 block_depth = src_params.block_size.depth;
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const size_t src_size =
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CalculateSize(true, bytes_per_pixel, width, height, depth, block_height, block_depth);
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const size_t src_layer_size =
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CalculateSize(true, bytes_per_pixel, width, height, 1, block_height, block_depth);
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if (read_buffer.size() < src_size) {
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read_buffer.resize(src_size);
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}
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if (write_buffer.size() < dst_size) {
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write_buffer.resize(dst_size);
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}
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memory_manager.ReadBlock(regs.offset_in, read_buffer.data(), src_size);
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memory_manager.ReadBlock(regs.offset_out, write_buffer.data(), dst_size);
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UnswizzleSubrect(regs.line_length_in, regs.line_count, regs.pitch_out, width, bytes_per_pixel,
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block_height, src_params.origin.x, src_params.origin.y, write_buffer.data(),
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read_buffer.data());
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memory_manager.WriteBlock(regs.offset_out, write_buffer.data(), dst_size);
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}
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void MaxwellDMA::CopyPitchToBlockLinear() {
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const auto& dst_params = regs.dst_params;
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const u32 bytes_per_pixel = regs.pitch_in / regs.line_length_in;
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const u32 width = dst_params.width;
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const u32 height = dst_params.height;
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const u32 depth = dst_params.depth;
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const u32 block_height = dst_params.block_size.height;
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const u32 block_depth = dst_params.block_size.depth;
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const size_t dst_size =
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CalculateSize(true, bytes_per_pixel, width, height, depth, block_height, block_depth);
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const size_t dst_layer_size =
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CalculateSize(true, bytes_per_pixel, width, height, 1, block_height, block_depth);
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const size_t src_size = static_cast<size_t>(regs.pitch_in) * regs.line_count;
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if (read_buffer.size() < src_size) {
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read_buffer.resize(src_size);
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}
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if (write_buffer.size() < dst_size) {
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write_buffer.resize(dst_size);
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}
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if (Settings::IsGPULevelExtreme()) {
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memory_manager.ReadBlock(regs.offset_in, read_buffer.data(), src_size);
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memory_manager.ReadBlock(regs.offset_out, write_buffer.data(), dst_size);
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} else {
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memory_manager.ReadBlockUnsafe(regs.offset_in, read_buffer.data(), src_size);
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memory_manager.ReadBlockUnsafe(regs.offset_out, write_buffer.data(), dst_size);
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}
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// If the input is linear and the output is tiled, swizzle the input and copy it over.
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if (regs.dst_params.block_size.depth > 0) {
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ASSERT(dst_params.layer == 0);
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SwizzleSliceToVoxel(regs.line_length_in, regs.line_count, regs.pitch_in, width, height,
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bytes_per_pixel, block_height, block_depth, dst_params.origin.x,
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dst_params.origin.y, write_buffer.data(), read_buffer.data());
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} else {
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SwizzleSubrect(regs.line_length_in, regs.line_count, regs.pitch_in, width, bytes_per_pixel,
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write_buffer.data() + dst_layer_size * dst_params.layer, read_buffer.data(),
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block_height, dst_params.origin.x, dst_params.origin.y);
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}
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memory_manager.WriteBlock(regs.offset_out, write_buffer.data(), dst_size);
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}
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void MaxwellDMA::FastCopyBlockLinearToPitch() {
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const u32 bytes_per_pixel = regs.pitch_out / regs.line_length_in;
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const size_t src_size = GOB_SIZE;
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const size_t dst_size = static_cast<size_t>(regs.pitch_out) * regs.line_count;
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u32 pos_x = regs.src_params.origin.x;
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u32 pos_y = regs.src_params.origin.y;
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const u64 offset = GetGOBOffset(regs.src_params.width, regs.src_params.height, pos_x, pos_y,
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regs.src_params.block_size.height, bytes_per_pixel);
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const u32 x_in_gob = 64 / bytes_per_pixel;
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pos_x = pos_x % x_in_gob;
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pos_y = pos_y % 8;
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if (read_buffer.size() < src_size) {
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read_buffer.resize(src_size);
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}
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if (write_buffer.size() < dst_size) {
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write_buffer.resize(dst_size);
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}
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if (Settings::IsGPULevelExtreme()) {
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memory_manager.ReadBlock(regs.offset_in + offset, read_buffer.data(), src_size);
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memory_manager.ReadBlock(regs.offset_out, write_buffer.data(), dst_size);
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} else {
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memory_manager.ReadBlockUnsafe(regs.offset_in + offset, read_buffer.data(), src_size);
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memory_manager.ReadBlockUnsafe(regs.offset_out, write_buffer.data(), dst_size);
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}
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UnswizzleSubrect(regs.line_length_in, regs.line_count, regs.pitch_out, regs.src_params.width,
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bytes_per_pixel, regs.src_params.block_size.height, pos_x, pos_y,
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write_buffer.data(), read_buffer.data());
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memory_manager.WriteBlock(regs.offset_out, write_buffer.data(), dst_size);
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}
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} // namespace Tegra::Engines
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