2018-02-05 00:08:20 +01:00
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using ChocolArm64.Decoder;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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2018-02-08 00:46:36 +01:00
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using System;
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using System.Reflection;
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2018-02-05 00:08:20 +01:00
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using System.Reflection.Emit;
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using static ChocolArm64.Instruction.AInstEmitAluHelper;
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namespace ChocolArm64.Instruction
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{
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static partial class AInstEmit
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{
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2018-02-24 22:47:08 +01:00
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public static void Adc(AILEmitterCtx Context) => EmitAdc(Context, false);
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public static void Adcs(AILEmitterCtx Context) => EmitAdc(Context, true);
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private static void EmitAdc(AILEmitterCtx Context, bool SetFlags)
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2018-02-08 00:46:36 +01:00
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{
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EmitDataLoadOpers(Context);
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Context.Emit(OpCodes.Add);
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Context.EmitLdflg((int)APState.CBit);
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Type[] MthdTypes = new Type[] { typeof(bool) };
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MethodInfo MthdInfo = typeof(Convert).GetMethod(nameof(Convert.ToInt32), MthdTypes);
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Context.EmitCall(MthdInfo);
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if (Context.CurrOp.RegisterSize != ARegisterSize.Int32)
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{
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2018-02-24 22:47:08 +01:00
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Context.Emit(OpCodes.Conv_U8);
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2018-02-08 00:46:36 +01:00
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}
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Context.Emit(OpCodes.Add);
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2018-02-24 22:47:08 +01:00
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if (SetFlags)
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{
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Context.EmitZNFlagCheck();
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2018-02-26 19:56:34 +01:00
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EmitAdcsCCheck(Context);
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2018-02-24 22:47:08 +01:00
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EmitAddsVCheck(Context);
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}
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2018-02-08 00:46:36 +01:00
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EmitDataStore(Context);
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}
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2018-02-05 00:08:20 +01:00
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public static void Add(AILEmitterCtx Context) => EmitDataOp(Context, OpCodes.Add);
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public static void Adds(AILEmitterCtx Context)
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{
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EmitDataLoadOpers(Context);
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Context.Emit(OpCodes.Add);
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Context.EmitZNFlagCheck();
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EmitAddsCCheck(Context);
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EmitAddsVCheck(Context);
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EmitDataStoreS(Context);
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}
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public static void And(AILEmitterCtx Context) => EmitDataOp(Context, OpCodes.And);
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public static void Ands(AILEmitterCtx Context)
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{
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EmitDataLoadOpers(Context);
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Context.Emit(OpCodes.And);
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2018-02-18 20:01:21 +01:00
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EmitZeroCVFlags(Context);
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2018-02-05 00:08:20 +01:00
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Context.EmitZNFlagCheck();
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EmitDataStoreS(Context);
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}
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public static void Asrv(AILEmitterCtx Context) => EmitDataOpShift(Context, OpCodes.Shr);
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public static void Bic(AILEmitterCtx Context) => EmitBic(Context, false);
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public static void Bics(AILEmitterCtx Context) => EmitBic(Context, true);
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private static void EmitBic(AILEmitterCtx Context, bool SetFlags)
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{
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EmitDataLoadOpers(Context);
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Context.Emit(OpCodes.Not);
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Context.Emit(OpCodes.And);
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if (SetFlags)
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{
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2018-02-18 20:01:21 +01:00
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EmitZeroCVFlags(Context);
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2018-02-05 00:08:20 +01:00
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Context.EmitZNFlagCheck();
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}
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EmitDataStore(Context, SetFlags);
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}
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2018-03-24 02:06:05 +01:00
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public static void Cls(AILEmitterCtx Context)
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{
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AOpCodeAlu Op = (AOpCodeAlu)Context.CurrOp;
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Context.EmitLdintzr(Op.Rn);
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Add Cls_V, Clz_V, Orn_V instructions. Add 18 Tests: And_V, Bic_V, Bif_V, Bit_V, Bsl_V, Cls_V, Clz_V, Orn_V, Orr_V. (#104)
* Update AOpCodeTable.cs
* Update AInstEmitSimdLogical.cs
* Update AInstEmitSimdArithmetic.cs
* Update ASoftFallback.cs
* Update AInstEmitAlu.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimdReg.cs
* Update CpuTestSimd.cs
2018-04-26 04:20:22 +02:00
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Context.EmitLdc_I4(Op.RegisterSize == ARegisterSize.Int32 ? 32 : 64);
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.CountLeadingSigns));
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2018-03-24 02:06:05 +01:00
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Context.EmitStintzr(Op.Rd);
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}
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2018-02-05 00:08:20 +01:00
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public static void Clz(AILEmitterCtx Context)
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{
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AOpCodeAlu Op = (AOpCodeAlu)Context.CurrOp;
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Context.EmitLdintzr(Op.Rn);
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Add Cls_V, Clz_V, Orn_V instructions. Add 18 Tests: And_V, Bic_V, Bif_V, Bit_V, Bsl_V, Cls_V, Clz_V, Orn_V, Orr_V. (#104)
* Update AOpCodeTable.cs
* Update AInstEmitSimdLogical.cs
* Update AInstEmitSimdArithmetic.cs
* Update ASoftFallback.cs
* Update AInstEmitAlu.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimdReg.cs
* Update CpuTestSimd.cs
2018-04-26 04:20:22 +02:00
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Context.EmitLdc_I4(Op.RegisterSize == ARegisterSize.Int32 ? 32 : 64);
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.CountLeadingZeros));
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2018-02-05 00:08:20 +01:00
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Context.EmitStintzr(Op.Rd);
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}
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2018-02-20 18:39:03 +01:00
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public static void Eon(AILEmitterCtx Context)
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{
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EmitDataLoadOpers(Context);
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Context.Emit(OpCodes.Not);
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Context.Emit(OpCodes.Xor);
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EmitDataStore(Context);
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}
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2018-02-05 00:08:20 +01:00
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public static void Eor(AILEmitterCtx Context) => EmitDataOp(Context, OpCodes.Xor);
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public static void Extr(AILEmitterCtx Context)
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{
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//TODO: Ensure that the Shift is valid for the Is64Bits.
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AOpCodeAluRs Op = (AOpCodeAluRs)Context.CurrOp;
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Context.EmitLdintzr(Op.Rm);
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if (Op.Shift > 0)
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{
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Context.EmitLdc_I4(Op.Shift);
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Context.Emit(OpCodes.Shr_Un);
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Context.EmitLdintzr(Op.Rn);
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Context.EmitLdc_I4(Op.GetBitsCount() - Op.Shift);
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Context.Emit(OpCodes.Shl);
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Context.Emit(OpCodes.Or);
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}
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EmitDataStore(Context);
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}
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public static void Lslv(AILEmitterCtx Context) => EmitDataOpShift(Context, OpCodes.Shl);
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public static void Lsrv(AILEmitterCtx Context) => EmitDataOpShift(Context, OpCodes.Shr_Un);
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2018-02-24 22:47:08 +01:00
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public static void Sbc(AILEmitterCtx Context) => EmitSbc(Context, false);
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public static void Sbcs(AILEmitterCtx Context) => EmitSbc(Context, true);
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private static void EmitSbc(AILEmitterCtx Context, bool SetFlags)
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2018-02-08 00:46:36 +01:00
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{
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EmitDataLoadOpers(Context);
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Context.Emit(OpCodes.Sub);
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Context.EmitLdflg((int)APState.CBit);
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Type[] MthdTypes = new Type[] { typeof(bool) };
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MethodInfo MthdInfo = typeof(Convert).GetMethod(nameof(Convert.ToInt32), MthdTypes);
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Context.EmitCall(MthdInfo);
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Context.EmitLdc_I4(1);
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Context.Emit(OpCodes.Xor);
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if (Context.CurrOp.RegisterSize != ARegisterSize.Int32)
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{
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2018-02-24 22:47:08 +01:00
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Context.Emit(OpCodes.Conv_U8);
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2018-02-08 00:46:36 +01:00
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}
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Context.Emit(OpCodes.Sub);
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2018-02-24 22:47:08 +01:00
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if (SetFlags)
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{
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Context.EmitZNFlagCheck();
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EmitSbcsCCheck(Context);
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EmitSubsVCheck(Context);
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}
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2018-02-08 00:46:36 +01:00
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EmitDataStore(Context);
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}
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2018-02-05 00:08:20 +01:00
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public static void Sub(AILEmitterCtx Context) => EmitDataOp(Context, OpCodes.Sub);
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public static void Subs(AILEmitterCtx Context)
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{
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Context.TryOptMarkCondWithoutCmp();
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EmitDataLoadOpers(Context);
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Context.Emit(OpCodes.Sub);
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Context.EmitZNFlagCheck();
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EmitSubsCCheck(Context);
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EmitSubsVCheck(Context);
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EmitDataStoreS(Context);
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2018-06-02 16:44:52 +02:00
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}
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2018-02-05 00:08:20 +01:00
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public static void Orn(AILEmitterCtx Context)
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{
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EmitDataLoadOpers(Context);
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Context.Emit(OpCodes.Not);
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Context.Emit(OpCodes.Or);
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EmitDataStore(Context);
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}
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public static void Orr(AILEmitterCtx Context) => EmitDataOp(Context, OpCodes.Or);
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public static void Rbit(AILEmitterCtx Context) => EmitFallback32_64(Context,
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nameof(ASoftFallback.ReverseBits32),
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nameof(ASoftFallback.ReverseBits64));
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public static void Rev16(AILEmitterCtx Context) => EmitFallback32_64(Context,
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nameof(ASoftFallback.ReverseBytes16_32),
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nameof(ASoftFallback.ReverseBytes16_64));
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public static void Rev32(AILEmitterCtx Context) => EmitFallback32_64(Context,
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nameof(ASoftFallback.ReverseBytes32_32),
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nameof(ASoftFallback.ReverseBytes32_64));
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2018-06-02 16:44:52 +02:00
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private static void EmitFallback32_64(AILEmitterCtx Context, string Name32, string Name64)
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2018-02-05 00:08:20 +01:00
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{
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AOpCodeAlu Op = (AOpCodeAlu)Context.CurrOp;
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Context.EmitLdintzr(Op.Rn);
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if (Op.RegisterSize == ARegisterSize.Int32)
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{
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ASoftFallback.EmitCall(Context, Name32);
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}
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else
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{
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ASoftFallback.EmitCall(Context, Name64);
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}
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Context.EmitStintzr(Op.Rd);
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}
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public static void Rev64(AILEmitterCtx Context)
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{
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AOpCodeAlu Op = (AOpCodeAlu)Context.CurrOp;
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Context.EmitLdintzr(Op.Rn);
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.ReverseBytes64));
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Context.EmitStintzr(Op.Rd);
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}
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public static void Rorv(AILEmitterCtx Context)
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{
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EmitDataLoadRn(Context);
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EmitDataLoadShift(Context);
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Context.Emit(OpCodes.Shr_Un);
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EmitDataLoadRn(Context);
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Context.EmitLdc_I4(Context.CurrOp.GetBitsCount());
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EmitDataLoadShift(Context);
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Context.Emit(OpCodes.Sub);
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Context.Emit(OpCodes.Shl);
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Context.Emit(OpCodes.Or);
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EmitDataStore(Context);
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}
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public static void Sdiv(AILEmitterCtx Context) => EmitDiv(Context, OpCodes.Div);
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public static void Udiv(AILEmitterCtx Context) => EmitDiv(Context, OpCodes.Div_Un);
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private static void EmitDiv(AILEmitterCtx Context, OpCode ILOp)
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{
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//If Rm == 0, Rd = 0 (division by zero).
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Context.EmitLdc_I(0);
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EmitDataLoadRm(Context);
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Context.EmitLdc_I(0);
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AILLabel BadDiv = new AILLabel();
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Context.Emit(OpCodes.Beq_S, BadDiv);
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Context.Emit(OpCodes.Pop);
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if (ILOp == OpCodes.Div)
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{
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//If Rn == INT_MIN && Rm == -1, Rd = INT_MIN (overflow).
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long IntMin = 1L << (Context.CurrOp.GetBitsCount() - 1);
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Context.EmitLdc_I(IntMin);
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EmitDataLoadRn(Context);
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Context.EmitLdc_I(IntMin);
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2018-06-02 16:44:52 +02:00
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2018-02-05 00:08:20 +01:00
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Context.Emit(OpCodes.Ceq);
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EmitDataLoadRm(Context);
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Context.EmitLdc_I(-1);
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Context.Emit(OpCodes.Ceq);
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Context.Emit(OpCodes.And);
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Context.Emit(OpCodes.Brtrue_S, BadDiv);
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Context.Emit(OpCodes.Pop);
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}
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EmitDataLoadRn(Context);
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EmitDataLoadRm(Context);
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Context.Emit(ILOp);
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Context.MarkLabel(BadDiv);
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EmitDataStore(Context);
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}
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private static void EmitDataOp(AILEmitterCtx Context, OpCode ILOp)
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{
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EmitDataLoadOpers(Context);
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Context.Emit(ILOp);
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EmitDataStore(Context);
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}
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private static void EmitDataOpShift(AILEmitterCtx Context, OpCode ILOp)
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{
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EmitDataLoadRn(Context);
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EmitDataLoadShift(Context);
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Context.Emit(ILOp);
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EmitDataStore(Context);
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}
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private static void EmitDataLoadShift(AILEmitterCtx Context)
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{
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EmitDataLoadRm(Context);
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Context.EmitLdc_I(Context.CurrOp.GetBitsCount() - 1);
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Context.Emit(OpCodes.And);
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//Note: Only 32-bits shift values are valid, so when the value is 64-bits
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//we need to cast it to a 32-bits integer. This is fine because we
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//AND the value and only keep the lower 5 or 6 bits anyway -- it
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//could very well fit on a byte.
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if (Context.CurrOp.RegisterSize != ARegisterSize.Int32)
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{
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Context.Emit(OpCodes.Conv_I4);
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}
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2018-02-18 20:01:21 +01:00
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}
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private static void EmitZeroCVFlags(AILEmitterCtx Context)
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{
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Context.EmitLdc_I4(0);
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2018-02-18 20:28:07 +01:00
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2018-02-18 20:01:21 +01:00
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Context.EmitStflg((int)APState.VBit);
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2018-02-18 20:28:07 +01:00
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Context.EmitLdc_I4(0);
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2018-02-18 20:01:21 +01:00
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Context.EmitStflg((int)APState.CBit);
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}
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2018-02-05 00:08:20 +01:00
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}
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2018-03-24 02:06:05 +01:00
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}
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