mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-08-18 22:58:43 +02:00
Get rid of Reflection.Emit dependency on CPU and Shader projects (#1626)
* Get rid of Reflection.Emit dependency on CPU and Shader projects * Remove useless private sets * Missed those due to the alignment
This commit is contained in:
parent
efa77a2415
commit
2f16491712
173 changed files with 1709 additions and 1417 deletions
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@ -14,7 +14,7 @@ namespace ARMeilleure.Decoders
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public bool TailCall { get; set; }
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public bool TailCall { get; set; }
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public bool Exit { get; set; }
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public bool Exit { get; set; }
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public List<OpCode> OpCodes { get; private set; }
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public List<OpCode> OpCodes { get; }
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public Block()
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public Block()
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{
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{
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@ -339,7 +339,7 @@ namespace ARMeilleure.Decoders
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if (makeOp != null)
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if (makeOp != null)
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{
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{
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return (OpCode)makeOp(inst, address, opCode);
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return makeOp(inst, address, opCode);
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}
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}
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else
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else
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{
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{
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@ -5,8 +5,8 @@ namespace ARMeilleure.Decoders
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{
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{
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class OpCode : IOpCode
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class OpCode : IOpCode
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{
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{
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public ulong Address { get; private set; }
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public ulong Address { get; }
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public int RawOpCode { get; private set; }
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public int RawOpCode { get; }
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public int OpCodeSizeInBytes { get; protected set; } = 4;
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public int OpCodeSizeInBytes { get; protected set; } = 4;
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@ -14,6 +14,8 @@ namespace ARMeilleure.Decoders
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public RegisterSize RegisterSize { get; protected set; }
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public RegisterSize RegisterSize { get; protected set; }
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public static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode(inst, address, opCode);
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public OpCode(InstDescriptor inst, ulong address, int opCode)
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public OpCode(InstDescriptor inst, ulong address, int opCode)
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{
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{
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Address = address;
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Address = address;
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@ -4,6 +4,8 @@ namespace ARMeilleure.Decoders
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{
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{
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public Condition Cond { get; protected set; }
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public Condition Cond { get; protected set; }
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32(inst, address, opCode);
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public OpCode32(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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public OpCode32(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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{
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RegisterSize = RegisterSize.Int32;
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RegisterSize = RegisterSize.Int32;
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@ -2,10 +2,12 @@ namespace ARMeilleure.Decoders
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{
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{
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class OpCode32Alu : OpCode32, IOpCode32Alu
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class OpCode32Alu : OpCode32, IOpCode32Alu
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{
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{
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public int Rd { get; private set; }
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public int Rd { get; }
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public int Rn { get; private set; }
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public int Rn { get; }
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public bool SetFlags { get; private set; }
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public bool SetFlags { get; }
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Alu(inst, address, opCode);
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public OpCode32Alu(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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public OpCode32Alu(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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{
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@ -2,16 +2,18 @@
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{
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{
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class OpCode32AluBf : OpCode32, IOpCode32AluBf
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class OpCode32AluBf : OpCode32, IOpCode32AluBf
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{
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{
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public int Rd { get; private set; }
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public int Rd { get; }
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public int Rn { get; private set; }
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public int Rn { get; }
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public int Msb { get; private set; }
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public int Msb { get; }
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public int Lsb { get; private set; }
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public int Lsb { get; }
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public int SourceMask => (int)(0xFFFFFFFF >> (31 - Msb));
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public int SourceMask => (int)(0xFFFFFFFF >> (31 - Msb));
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public int DestMask => SourceMask & (int)(0xFFFFFFFF << Lsb);
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public int DestMask => SourceMask & (int)(0xFFFFFFFF << Lsb);
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluBf(inst, address, opCode);
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public OpCode32AluBf(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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public OpCode32AluBf(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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{
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Rd = (opCode >> 12) & 0xf;
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Rd = (opCode >> 12) & 0xf;
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@ -4,9 +4,11 @@ namespace ARMeilleure.Decoders
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{
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{
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class OpCode32AluImm : OpCode32Alu
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class OpCode32AluImm : OpCode32Alu
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{
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{
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public int Immediate { get; private set; }
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public int Immediate { get; }
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public bool IsRotated { get; private set; }
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public bool IsRotated { get; }
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluImm(inst, address, opCode);
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public OpCode32AluImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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public OpCode32AluImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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{
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@ -2,7 +2,9 @@
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{
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{
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class OpCode32AluImm16 : OpCode32Alu
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class OpCode32AluImm16 : OpCode32Alu
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{
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{
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public int Immediate { get; private set; }
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public int Immediate { get; }
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluImm16(inst, address, opCode);
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public OpCode32AluImm16(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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public OpCode32AluImm16(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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{
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@ -2,15 +2,17 @@
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{
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{
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class OpCode32AluMla : OpCode32, IOpCode32AluReg
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class OpCode32AluMla : OpCode32, IOpCode32AluReg
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{
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{
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public int Rn { get; private set; }
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public int Rn { get; }
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public int Rm { get; private set; }
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public int Rm { get; }
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public int Ra { get; private set; }
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public int Ra { get; }
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public int Rd { get; private set; }
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public int Rd { get; }
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public bool NHigh { get; private set; }
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public bool NHigh { get; }
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public bool MHigh { get; private set; }
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public bool MHigh { get; }
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public bool R { get; private set; }
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public bool R { get; }
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public bool SetFlags { get; private set; }
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public bool SetFlags { get; }
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluMla(inst, address, opCode);
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public OpCode32AluMla(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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public OpCode32AluMla(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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{
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{
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{
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class OpCode32AluReg : OpCode32Alu, IOpCode32AluReg
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class OpCode32AluReg : OpCode32Alu, IOpCode32AluReg
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{
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{
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public int Rm { get; private set; }
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public int Rm { get; }
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluReg(inst, address, opCode);
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public OpCode32AluReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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public OpCode32AluReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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{
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@ -2,10 +2,12 @@ namespace ARMeilleure.Decoders
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{
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{
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class OpCode32AluRsImm : OpCode32Alu
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class OpCode32AluRsImm : OpCode32Alu
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{
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{
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public int Rm { get; private set; }
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public int Rm { get; }
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public int Immediate { get; private set; }
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public int Immediate { get; }
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public ShiftType ShiftType { get; private set; }
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public ShiftType ShiftType { get; }
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluRsImm(inst, address, opCode);
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public OpCode32AluRsImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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public OpCode32AluRsImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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{
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{
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{
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class OpCode32AluRsReg : OpCode32Alu
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class OpCode32AluRsReg : OpCode32Alu
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{
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{
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public int Rm { get; private set; }
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public int Rm { get; }
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public int Rs { get; private set; }
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public int Rs { get; }
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public ShiftType ShiftType { get; private set; }
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public ShiftType ShiftType { get; }
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluRsReg(inst, address, opCode);
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public OpCode32AluRsReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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public OpCode32AluRsReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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{
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{
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{
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class OpCode32AluUmull : OpCode32
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class OpCode32AluUmull : OpCode32
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{
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{
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public int RdLo { get; private set; }
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public int RdLo { get; }
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public int RdHi { get; private set; }
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public int RdHi { get; }
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public int Rn { get; private set; }
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public int Rn { get; }
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public int Rm { get; private set; }
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public int Rm { get; }
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public bool NHigh { get; private set; }
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public bool NHigh { get; }
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public bool MHigh { get; private set; }
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public bool MHigh { get; }
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public bool SetFlags { get; private set; }
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public bool SetFlags { get; }
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public DataOp DataOp { get; private set; }
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public DataOp DataOp { get; }
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluUmull(inst, address, opCode);
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public OpCode32AluUmull(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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public OpCode32AluUmull(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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{
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@ -4,10 +4,12 @@ namespace ARMeilleure.Decoders
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{
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{
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class OpCode32AluUx : OpCode32AluReg, IOpCode32AluUx
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class OpCode32AluUx : OpCode32AluReg, IOpCode32AluUx
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{
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{
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public int Rotate { get; private set; }
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public int Rotate { get; }
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public int RotateBits => Rotate * 8;
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public int RotateBits => Rotate * 8;
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public bool Add => Rn != RegisterAlias.Aarch32Pc;
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public bool Add => Rn != RegisterAlias.Aarch32Pc;
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluUx(inst, address, opCode);
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public OpCode32AluUx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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public OpCode32AluUx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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{
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Rotate = (opCode >> 10) & 0x3;
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Rotate = (opCode >> 10) & 0x3;
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@ -2,7 +2,9 @@ namespace ARMeilleure.Decoders
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{
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{
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class OpCode32BImm : OpCode32, IOpCode32BImm
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class OpCode32BImm : OpCode32, IOpCode32BImm
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{
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{
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public long Immediate { get; private set; }
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public long Immediate { get; }
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32BImm(inst, address, opCode);
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public OpCode32BImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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public OpCode32BImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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{
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@ -2,7 +2,9 @@ namespace ARMeilleure.Decoders
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{
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{
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class OpCode32BReg : OpCode32, IOpCode32BReg
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class OpCode32BReg : OpCode32, IOpCode32BReg
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{
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{
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public int Rm { get; private set; }
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public int Rm { get; }
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32BReg(inst, address, opCode);
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public OpCode32BReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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public OpCode32BReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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{
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{
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{
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class OpCode32Exception : OpCode32
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class OpCode32Exception : OpCode32
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{
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{
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public int Id { get; private set; }
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public int Id { get; }
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Exception(inst, address, opCode);
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public OpCode32Exception(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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public OpCode32Exception(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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{
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class OpCode32Mem : OpCode32, IOpCode32Mem
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class OpCode32Mem : OpCode32, IOpCode32Mem
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{
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{
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public int Rt { get; protected set; }
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public int Rt { get; protected set; }
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public int Rn { get; private set; }
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public int Rn { get; }
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public int Immediate { get; protected set; }
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public int Immediate { get; protected set; }
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public bool Index { get; private set; }
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public bool Index { get; }
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public bool Add { get; private set; }
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public bool Add { get; }
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public bool WBack { get; private set; }
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public bool WBack { get; }
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public bool Unprivileged { get; private set; }
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public bool Unprivileged { get; }
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public bool IsLoad { get; private set; }
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public bool IsLoad { get; }
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Mem(inst, address, opCode);
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public OpCode32Mem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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public OpCode32Mem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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{
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{
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{
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class OpCode32MemImm : OpCode32Mem
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class OpCode32MemImm : OpCode32Mem
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{
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{
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemImm(inst, address, opCode);
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public OpCode32MemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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public OpCode32MemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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{
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Immediate = opCode & 0xfff;
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Immediate = opCode & 0xfff;
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{
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{
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class OpCode32MemImm8 : OpCode32Mem
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class OpCode32MemImm8 : OpCode32Mem
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{
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{
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemImm8(inst, address, opCode);
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public OpCode32MemImm8(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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public OpCode32MemImm8(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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{
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int imm4L = (opCode >> 0) & 0xf;
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int imm4L = (opCode >> 0) & 0xf;
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{
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{
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class OpCode32MemLdEx : OpCode32Mem, IOpCode32MemEx
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class OpCode32MemLdEx : OpCode32Mem, IOpCode32MemEx
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{
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{
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public int Rd { get; private set; }
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public int Rd { get; }
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemLdEx(inst, address, opCode);
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public OpCode32MemLdEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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public OpCode32MemLdEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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{
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@ -2,13 +2,15 @@ namespace ARMeilleure.Decoders
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{
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{
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class OpCode32MemMult : OpCode32, IOpCode32MemMult
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class OpCode32MemMult : OpCode32, IOpCode32MemMult
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{
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{
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public int Rn { get; private set; }
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public int Rn { get; }
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public int RegisterMask { get; private set; }
|
public int RegisterMask { get; }
|
||||||
public int Offset { get; private set; }
|
public int Offset { get; }
|
||||||
public int PostOffset { get; private set; }
|
public int PostOffset { get; }
|
||||||
|
|
||||||
public bool IsLoad { get; private set; }
|
public bool IsLoad { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemMult(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32MemMult(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32MemMult(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,7 +2,9 @@
|
||||||
{
|
{
|
||||||
class OpCode32MemReg : OpCode32Mem
|
class OpCode32MemReg : OpCode32Mem
|
||||||
{
|
{
|
||||||
public int Rm { get; private set; }
|
public int Rm { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemReg(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32MemReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32MemReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,8 +2,10 @@
|
||||||
{
|
{
|
||||||
class OpCode32MemRsImm : OpCode32Mem
|
class OpCode32MemRsImm : OpCode32Mem
|
||||||
{
|
{
|
||||||
public int Rm { get; private set; }
|
public int Rm { get; }
|
||||||
public ShiftType ShiftType { get; private set; }
|
public ShiftType ShiftType { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemRsImm(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32MemRsImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32MemRsImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,7 +2,9 @@
|
||||||
{
|
{
|
||||||
class OpCode32MemStEx : OpCode32Mem, IOpCode32MemEx
|
class OpCode32MemStEx : OpCode32Mem, IOpCode32MemEx
|
||||||
{
|
{
|
||||||
public int Rd { get; private set; }
|
public int Rd { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemStEx(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32MemStEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32MemStEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,12 +2,14 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCode32Sat : OpCode32
|
class OpCode32Sat : OpCode32
|
||||||
{
|
{
|
||||||
public int Rn { get; private set; }
|
public int Rn { get; }
|
||||||
public int Imm5 { get; private set; }
|
public int Imm5 { get; }
|
||||||
public int Rd { get; private set; }
|
public int Rd { get; }
|
||||||
public int SatImm { get; private set; }
|
public int SatImm { get; }
|
||||||
|
|
||||||
public ShiftType ShiftType { get; private set; }
|
public ShiftType ShiftType { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Sat(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32Sat(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32Sat(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,9 +2,11 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCode32Sat16 : OpCode32
|
class OpCode32Sat16 : OpCode32
|
||||||
{
|
{
|
||||||
public int Rn { get; private set; }
|
public int Rn { get; }
|
||||||
public int Rd { get; private set; }
|
public int Rd { get; }
|
||||||
public int SatImm { get; private set; }
|
public int SatImm { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Sat16(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32Sat16(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32Sat16(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -5,7 +5,9 @@
|
||||||
public int Opc { get; protected set; }
|
public int Opc { get; protected set; }
|
||||||
public bool Q { get; protected set; }
|
public bool Q { get; protected set; }
|
||||||
public bool F { get; protected set; }
|
public bool F { get; protected set; }
|
||||||
public bool U { get; private set; }
|
public bool U { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Simd(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32Simd(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32Simd(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -5,6 +5,8 @@
|
||||||
/// </summary>
|
/// </summary>
|
||||||
class OpCode32SimdBinary : OpCode32SimdReg
|
class OpCode32SimdBinary : OpCode32SimdReg
|
||||||
{
|
{
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdBinary(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32SimdBinary(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32SimdBinary(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
Size = 3;
|
Size = 3;
|
||||||
|
|
|
@ -2,6 +2,8 @@
|
||||||
{
|
{
|
||||||
class OpCode32SimdCmpZ : OpCode32Simd
|
class OpCode32SimdCmpZ : OpCode32Simd
|
||||||
{
|
{
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCmpZ(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32SimdCmpZ(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32SimdCmpZ(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
Size = (opCode >> 18) & 0x3;
|
Size = (opCode >> 18) & 0x3;
|
||||||
|
|
|
@ -2,6 +2,8 @@
|
||||||
{
|
{
|
||||||
class OpCode32SimdCvtFI : OpCode32SimdS
|
class OpCode32SimdCvtFI : OpCode32SimdS
|
||||||
{
|
{
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCvtFI(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32SimdCvtFI(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32SimdCvtFI(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
Opc = (opCode >> 7) & 0x1;
|
Opc = (opCode >> 7) & 0x1;
|
||||||
|
|
|
@ -2,7 +2,9 @@
|
||||||
{
|
{
|
||||||
class OpCode32SimdDupElem : OpCode32Simd
|
class OpCode32SimdDupElem : OpCode32Simd
|
||||||
{
|
{
|
||||||
public int Index { get; private set; }
|
public int Index { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdDupElem(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32SimdDupElem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32SimdDupElem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,10 +2,12 @@
|
||||||
{
|
{
|
||||||
class OpCode32SimdDupGP : OpCode32, IOpCode32Simd
|
class OpCode32SimdDupGP : OpCode32, IOpCode32Simd
|
||||||
{
|
{
|
||||||
public int Size { get; private set; }
|
public int Size { get; }
|
||||||
public int Vd { get; private set; }
|
public int Vd { get; }
|
||||||
public int Rt { get; private set; }
|
public int Rt { get; }
|
||||||
public bool Q { get; private set; }
|
public bool Q { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdDupGP(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32SimdDupGP(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32SimdDupGP(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,7 +2,9 @@
|
||||||
{
|
{
|
||||||
class OpCode32SimdExt : OpCode32SimdReg
|
class OpCode32SimdExt : OpCode32SimdReg
|
||||||
{
|
{
|
||||||
public int Immediate { get; private set; }
|
public int Immediate { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdExt(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32SimdExt(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32SimdExt(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,10 +2,12 @@
|
||||||
{
|
{
|
||||||
class OpCode32SimdImm : OpCode32SimdBase, IOpCode32SimdImm
|
class OpCode32SimdImm : OpCode32SimdBase, IOpCode32SimdImm
|
||||||
{
|
{
|
||||||
public bool Q { get; private set; }
|
public bool Q { get; }
|
||||||
public long Immediate { get; private set; }
|
public long Immediate { get; }
|
||||||
public int Elems => GetBytesCount() >> Size;
|
public int Elems => GetBytesCount() >> Size;
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdImm(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32SimdImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32SimdImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
Vd = (opCode >> 12) & 0xf;
|
Vd = (opCode >> 12) & 0xf;
|
||||||
|
|
|
@ -2,10 +2,12 @@
|
||||||
{
|
{
|
||||||
class OpCode32SimdImm44 : OpCode32, IOpCode32SimdImm
|
class OpCode32SimdImm44 : OpCode32, IOpCode32SimdImm
|
||||||
{
|
{
|
||||||
public int Vd { get; private set; }
|
public int Vd { get; }
|
||||||
public long Immediate { get; private set; }
|
public long Immediate { get; }
|
||||||
public int Size { get; private set; }
|
public int Size { get; }
|
||||||
public int Elems { get; private set; }
|
public int Elems { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdImm44(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32SimdImm44(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32SimdImm44(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,7 +2,9 @@
|
||||||
{
|
{
|
||||||
class OpCode32SimdLong : OpCode32SimdBase
|
class OpCode32SimdLong : OpCode32SimdBase
|
||||||
{
|
{
|
||||||
public bool U { get; private set; }
|
public bool U { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdLong(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32SimdLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32SimdLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,11 +2,13 @@
|
||||||
{
|
{
|
||||||
class OpCode32SimdMemImm : OpCode32, IOpCode32Simd
|
class OpCode32SimdMemImm : OpCode32, IOpCode32Simd
|
||||||
{
|
{
|
||||||
public int Vd { get; private set; }
|
public int Vd { get; }
|
||||||
public int Rn { get; private set; }
|
public int Rn { get; }
|
||||||
public int Size { get; private set; }
|
public int Size { get; }
|
||||||
public bool Add { get; private set; }
|
public bool Add { get; }
|
||||||
public int Immediate { get; private set; }
|
public int Immediate { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemImm(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32SimdMemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32SimdMemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,15 +2,17 @@
|
||||||
{
|
{
|
||||||
class OpCode32SimdMemMult : OpCode32
|
class OpCode32SimdMemMult : OpCode32
|
||||||
{
|
{
|
||||||
public int Rn { get; private set; }
|
public int Rn { get; }
|
||||||
public int Vd { get; private set; }
|
public int Vd { get; }
|
||||||
|
|
||||||
public int RegisterRange { get; private set; }
|
public int RegisterRange { get; }
|
||||||
public int Offset { get; private set; }
|
public int Offset { get; }
|
||||||
public int PostOffset { get; private set; }
|
public int PostOffset { get; }
|
||||||
public bool IsLoad { get; private set; }
|
public bool IsLoad { get; }
|
||||||
public bool DoubleWidth { get; private set; }
|
public bool DoubleWidth { get; }
|
||||||
public bool Add { get; private set; }
|
public bool Add { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemMult(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32SimdMemMult(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32SimdMemMult(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -13,16 +13,18 @@ namespace ARMeilleure.Decoders
|
||||||
1, 1, 1, 1
|
1, 1, 1, 1
|
||||||
};
|
};
|
||||||
|
|
||||||
public int Vd { get; private set; }
|
public int Vd { get; }
|
||||||
public int Rn { get; private set; }
|
public int Rn { get; }
|
||||||
public int Rm { get; private set; }
|
public int Rm { get; }
|
||||||
public int Align { get; private set; }
|
public int Align { get; }
|
||||||
public bool WBack { get; private set; }
|
public bool WBack { get; }
|
||||||
public bool RegisterIndex { get; private set; }
|
public bool RegisterIndex { get; }
|
||||||
public int Size { get; private set; }
|
public int Size { get; }
|
||||||
public int Elems => 8 >> Size;
|
public int Elems => 8 >> Size;
|
||||||
public int Regs { get; private set; }
|
public int Regs { get; }
|
||||||
public int Increment { get; private set; }
|
public int Increment { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemPair(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32SimdMemPair(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32SimdMemPair(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -4,16 +4,18 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCode32SimdMemSingle : OpCode32, IOpCode32Simd
|
class OpCode32SimdMemSingle : OpCode32, IOpCode32Simd
|
||||||
{
|
{
|
||||||
public int Vd { get; private set; }
|
public int Vd { get; }
|
||||||
public int Rn { get; private set; }
|
public int Rn { get; }
|
||||||
public int Rm { get; private set; }
|
public int Rm { get; }
|
||||||
public int IndexAlign { get; private set; }
|
public int IndexAlign { get; }
|
||||||
public int Index { get; private set; }
|
public int Index { get; }
|
||||||
public bool WBack { get; private set; }
|
public bool WBack { get; }
|
||||||
public bool RegisterIndex { get; private set; }
|
public bool RegisterIndex { get; }
|
||||||
public int Size { get; private set; }
|
public int Size { get; }
|
||||||
public bool Replicate { get; private set; }
|
public bool Replicate { get; }
|
||||||
public int Increment { get; private set; }
|
public int Increment { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemSingle(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32SimdMemSingle(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32SimdMemSingle(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -4,12 +4,14 @@
|
||||||
{
|
{
|
||||||
public int Size => 2;
|
public int Size => 2;
|
||||||
|
|
||||||
public int Vn { get; private set; }
|
public int Vn { get; }
|
||||||
public int Rt { get; private set; }
|
public int Rt { get; }
|
||||||
public int Op { get; private set; }
|
public int Op { get; }
|
||||||
|
|
||||||
public int Opc1 { get; private set; }
|
public int Opc1 { get; }
|
||||||
public int Opc2 { get; private set; }
|
public int Opc2 { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGp(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32SimdMovGp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32SimdMovGp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -4,10 +4,12 @@
|
||||||
{
|
{
|
||||||
public int Size => 3;
|
public int Size => 3;
|
||||||
|
|
||||||
public int Vm { get; private set; }
|
public int Vm { get; }
|
||||||
public int Rt { get; private set; }
|
public int Rt { get; }
|
||||||
public int Rt2 { get; private set; }
|
public int Rt2 { get; }
|
||||||
public int Op { get; private set; }
|
public int Op { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGpDouble(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32SimdMovGpDouble(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32SimdMovGpDouble(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,14 +2,16 @@
|
||||||
{
|
{
|
||||||
class OpCode32SimdMovGpElem : OpCode32, IOpCode32Simd
|
class OpCode32SimdMovGpElem : OpCode32, IOpCode32Simd
|
||||||
{
|
{
|
||||||
public int Size { get; private set; }
|
public int Size { get; }
|
||||||
|
|
||||||
public int Vd { get; private set; }
|
public int Vd { get; }
|
||||||
public int Rt { get; private set; }
|
public int Rt { get; }
|
||||||
public int Op { get; private set; }
|
public int Op { get; }
|
||||||
public bool U { get; private set; }
|
public bool U { get; }
|
||||||
|
|
||||||
public int Index { get; private set; }
|
public int Index { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGpElem(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32SimdMovGpElem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32SimdMovGpElem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,12 +2,14 @@
|
||||||
{
|
{
|
||||||
class OpCode32SimdReg : OpCode32Simd
|
class OpCode32SimdReg : OpCode32Simd
|
||||||
{
|
{
|
||||||
public int Vn { get; private set; }
|
public int Vn { get; }
|
||||||
|
|
||||||
public int Qn => GetQuadwordIndex(Vn);
|
public int Qn => GetQuadwordIndex(Vn);
|
||||||
public int In => GetQuadwordSubindex(Vn) << (3 - Size);
|
public int In => GetQuadwordSubindex(Vn) << (3 - Size);
|
||||||
public int Fn => GetQuadwordSubindex(Vn) << (1 - (Size & 1));
|
public int Fn => GetQuadwordSubindex(Vn) << (1 - (Size & 1));
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdReg(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32SimdReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32SimdReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
Vn = ((opCode >> 3) & 0x10) | ((opCode >> 16) & 0xf);
|
Vn = ((opCode >> 3) & 0x10) | ((opCode >> 16) & 0xf);
|
||||||
|
|
|
@ -2,6 +2,8 @@
|
||||||
{
|
{
|
||||||
class OpCode32SimdRegElem : OpCode32SimdReg
|
class OpCode32SimdRegElem : OpCode32SimdReg
|
||||||
{
|
{
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegElem(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32SimdRegElem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32SimdRegElem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
Q = ((opCode >> 24) & 0x1) != 0;
|
Q = ((opCode >> 24) & 0x1) != 0;
|
||||||
|
|
|
@ -2,6 +2,8 @@
|
||||||
{
|
{
|
||||||
class OpCode32SimdRegElemLong : OpCode32SimdRegElem
|
class OpCode32SimdRegElemLong : OpCode32SimdRegElem
|
||||||
{
|
{
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegElemLong(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32SimdRegElemLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32SimdRegElemLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
Q = false;
|
Q = false;
|
||||||
|
|
|
@ -2,7 +2,9 @@
|
||||||
{
|
{
|
||||||
class OpCode32SimdRegLong : OpCode32SimdReg
|
class OpCode32SimdRegLong : OpCode32SimdReg
|
||||||
{
|
{
|
||||||
public bool Polynomial { get; private set; }
|
public bool Polynomial { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegLong(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32SimdRegLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32SimdRegLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,7 +2,9 @@
|
||||||
{
|
{
|
||||||
class OpCode32SimdRegS : OpCode32SimdS
|
class OpCode32SimdRegS : OpCode32SimdS
|
||||||
{
|
{
|
||||||
public int Vn { get; private set; }
|
public int Vn { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegS(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32SimdRegS(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32SimdRegS(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,6 +2,8 @@
|
||||||
{
|
{
|
||||||
class OpCode32SimdRegWide : OpCode32SimdReg
|
class OpCode32SimdRegWide : OpCode32SimdReg
|
||||||
{
|
{
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegWide(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32SimdRegWide(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32SimdRegWide(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
Q = false;
|
Q = false;
|
||||||
|
|
|
@ -2,6 +2,8 @@
|
||||||
{
|
{
|
||||||
class OpCode32SimdRev : OpCode32SimdCmpZ
|
class OpCode32SimdRev : OpCode32SimdCmpZ
|
||||||
{
|
{
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRev(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32SimdRev(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32SimdRev(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
if (Opc + Size >= 3)
|
if (Opc + Size >= 3)
|
||||||
|
|
|
@ -5,9 +5,11 @@
|
||||||
public int Vd { get; protected set; }
|
public int Vd { get; protected set; }
|
||||||
public int Vm { get; protected set; }
|
public int Vm { get; protected set; }
|
||||||
public int Opc { get; protected set; } // "with_zero" (Opc<1>) [Vcmp, Vcmpe].
|
public int Opc { get; protected set; } // "with_zero" (Opc<1>) [Vcmp, Vcmpe].
|
||||||
public int Opc2 { get; private set; } // opc2 or RM (opc2<1:0>) [Vcvt, Vrint].
|
public int Opc2 { get; } // opc2 or RM (opc2<1:0>) [Vcvt, Vrint].
|
||||||
public int Size { get; protected set; }
|
public int Size { get; protected set; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdS(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32SimdS(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32SimdS(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
Opc = (opCode >> 15) & 0x3;
|
Opc = (opCode >> 15) & 0x3;
|
||||||
|
|
|
@ -2,7 +2,9 @@
|
||||||
{
|
{
|
||||||
class OpCode32SimdSel : OpCode32SimdRegS
|
class OpCode32SimdSel : OpCode32SimdRegS
|
||||||
{
|
{
|
||||||
public OpCode32SimdSelMode Cc { get; private set; }
|
public OpCode32SimdSelMode Cc { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSel(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32SimdSel(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32SimdSel(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,7 +2,9 @@
|
||||||
{
|
{
|
||||||
class OpCode32SimdShImm : OpCode32Simd
|
class OpCode32SimdShImm : OpCode32Simd
|
||||||
{
|
{
|
||||||
public int Shift { get; private set; }
|
public int Shift { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImm(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32SimdShImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32SimdShImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,7 +2,9 @@
|
||||||
{
|
{
|
||||||
class OpCode32SimdShImmLong : OpCode32Simd
|
class OpCode32SimdShImmLong : OpCode32Simd
|
||||||
{
|
{
|
||||||
public int Shift { get; private set; }
|
public int Shift { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImmLong(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32SimdShImmLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32SimdShImmLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,6 +2,8 @@
|
||||||
{
|
{
|
||||||
class OpCode32SimdShImmNarrow : OpCode32SimdShImm
|
class OpCode32SimdShImmNarrow : OpCode32SimdShImm
|
||||||
{
|
{
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImmNarrow(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32SimdShImmNarrow(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
|
public OpCode32SimdShImmNarrow(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
|
@ -2,8 +2,10 @@
|
||||||
{
|
{
|
||||||
class OpCode32SimdSpecial : OpCode32
|
class OpCode32SimdSpecial : OpCode32
|
||||||
{
|
{
|
||||||
public int Rt { get; private set; }
|
public int Rt { get; }
|
||||||
public int Sreg { get; private set; }
|
public int Sreg { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSpecial(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32SimdSpecial(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32SimdSpecial(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,6 +2,8 @@
|
||||||
{
|
{
|
||||||
class OpCode32SimdSqrte : OpCode32Simd
|
class OpCode32SimdSqrte : OpCode32Simd
|
||||||
{
|
{
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSqrte(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32SimdSqrte(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32SimdSqrte(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
Size = (opCode >> 18) & 0x1;
|
Size = (opCode >> 18) & 0x1;
|
||||||
|
|
|
@ -2,7 +2,9 @@
|
||||||
{
|
{
|
||||||
class OpCode32SimdTbl : OpCode32SimdReg
|
class OpCode32SimdTbl : OpCode32SimdReg
|
||||||
{
|
{
|
||||||
public int Length { get; private set; }
|
public int Length { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdTbl(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32SimdTbl(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32SimdTbl(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,14 +2,16 @@
|
||||||
{
|
{
|
||||||
class OpCode32System : OpCode32
|
class OpCode32System : OpCode32
|
||||||
{
|
{
|
||||||
public int Opc1 { get; private set; }
|
public int Opc1 { get; }
|
||||||
public int CRn { get; private set; }
|
public int CRn { get; }
|
||||||
public int Rt { get; private set; }
|
public int Rt { get; }
|
||||||
public int Opc2 { get; private set; }
|
public int Opc2 { get; }
|
||||||
public int CRm { get; private set; }
|
public int CRm { get; }
|
||||||
public int MrrcOp { get; private set; }
|
public int MrrcOp { get; }
|
||||||
|
|
||||||
public int Coproc { get; private set; }
|
public int Coproc { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32System(inst, address, opCode);
|
||||||
|
|
||||||
public OpCode32System(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCode32System(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,11 +2,13 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeAdr : OpCode
|
class OpCodeAdr : OpCode
|
||||||
{
|
{
|
||||||
public int Rd { get; private set; }
|
public int Rd { get; }
|
||||||
|
|
||||||
public long Immediate { get; private set; }
|
public long Immediate { get; }
|
||||||
|
|
||||||
public OpCodeAdr(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAdr(inst, address, opCode);
|
||||||
|
|
||||||
|
public OpCodeAdr(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
Rd = opCode & 0x1f;
|
Rd = opCode & 0x1f;
|
||||||
|
|
||||||
|
|
|
@ -3,9 +3,11 @@ namespace ARMeilleure.Decoders
|
||||||
class OpCodeAlu : OpCode, IOpCodeAlu
|
class OpCodeAlu : OpCode, IOpCodeAlu
|
||||||
{
|
{
|
||||||
public int Rd { get; protected set; }
|
public int Rd { get; protected set; }
|
||||||
public int Rn { get; private set; }
|
public int Rn { get; }
|
||||||
|
|
||||||
public DataOp DataOp { get; private set; }
|
public DataOp DataOp { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAlu(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeAlu(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeAlu(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,7 +2,9 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeAluBinary : OpCodeAlu
|
class OpCodeAluBinary : OpCodeAlu
|
||||||
{
|
{
|
||||||
public int Rm { get; private set; }
|
public int Rm { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAluBinary(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeAluBinary(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeAluBinary(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -4,7 +4,9 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeAluImm : OpCodeAlu, IOpCodeAluImm
|
class OpCodeAluImm : OpCodeAlu, IOpCodeAluImm
|
||||||
{
|
{
|
||||||
public long Immediate { get; private set; }
|
public long Immediate { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAluImm(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeAluImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeAluImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,10 +2,12 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeAluRs : OpCodeAlu, IOpCodeAluRs
|
class OpCodeAluRs : OpCodeAlu, IOpCodeAluRs
|
||||||
{
|
{
|
||||||
public int Shift { get; private set; }
|
public int Shift { get; }
|
||||||
public int Rm { get; private set; }
|
public int Rm { get; }
|
||||||
|
|
||||||
public ShiftType ShiftType { get; private set; }
|
public ShiftType ShiftType { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAluRs(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeAluRs(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeAluRs(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,10 +2,12 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeAluRx : OpCodeAlu, IOpCodeAluRx
|
class OpCodeAluRx : OpCodeAlu, IOpCodeAluRx
|
||||||
{
|
{
|
||||||
public int Shift { get; private set; }
|
public int Shift { get; }
|
||||||
public int Rm { get; private set; }
|
public int Rm { get; }
|
||||||
|
|
||||||
public IntType IntType { get; private set; }
|
public IntType IntType { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAluRx(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeAluRx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeAluRx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -4,6 +4,8 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
public long Immediate { get; protected set; }
|
public long Immediate { get; protected set; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImm(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeBImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
|
public OpCodeBImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
|
||||||
}
|
}
|
||||||
}
|
}
|
|
@ -2,6 +2,8 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeBImmAl : OpCodeBImm
|
class OpCodeBImmAl : OpCodeBImm
|
||||||
{
|
{
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImmAl(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeBImmAl(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeBImmAl(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
Immediate = (long)address + DecoderHelper.DecodeImm26_2(opCode);
|
Immediate = (long)address + DecoderHelper.DecodeImm26_2(opCode);
|
||||||
|
|
|
@ -2,7 +2,9 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeBImmCmp : OpCodeBImm
|
class OpCodeBImmCmp : OpCodeBImm
|
||||||
{
|
{
|
||||||
public int Rt { get; private set; }
|
public int Rt { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImmCmp(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeBImmCmp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeBImmCmp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,7 +2,9 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeBImmCond : OpCodeBImm, IOpCodeCond
|
class OpCodeBImmCond : OpCodeBImm, IOpCodeCond
|
||||||
{
|
{
|
||||||
public Condition Cond { get; private set; }
|
public Condition Cond { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImmCond(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeBImmCond(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeBImmCond(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,8 +2,10 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeBImmTest : OpCodeBImm
|
class OpCodeBImmTest : OpCodeBImm
|
||||||
{
|
{
|
||||||
public int Rt { get; private set; }
|
public int Rt { get; }
|
||||||
public int Bit { get; private set; }
|
public int Bit { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImmTest(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeBImmTest(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeBImmTest(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,7 +2,9 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeBReg : OpCode
|
class OpCodeBReg : OpCode
|
||||||
{
|
{
|
||||||
public int Rn { get; private set; }
|
public int Rn { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBReg(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeBReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeBReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,10 +2,12 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeBfm : OpCodeAlu
|
class OpCodeBfm : OpCodeAlu
|
||||||
{
|
{
|
||||||
public long WMask { get; private set; }
|
public long WMask { get; }
|
||||||
public long TMask { get; private set; }
|
public long TMask { get; }
|
||||||
public int Pos { get; private set; }
|
public int Pos { get; }
|
||||||
public int Shift { get; private set; }
|
public int Shift { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBfm(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeBfm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeBfm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -4,10 +4,12 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeCcmp : OpCodeAlu, IOpCodeCond
|
class OpCodeCcmp : OpCodeAlu, IOpCodeCond
|
||||||
{
|
{
|
||||||
public int Nzcv { get; private set; }
|
public int Nzcv { get; }
|
||||||
protected int RmImm;
|
protected int RmImm;
|
||||||
|
|
||||||
public Condition Cond { get; private set; }
|
public Condition Cond { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeCcmp(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeCcmp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeCcmp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -4,6 +4,8 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
public long Immediate => RmImm;
|
public long Immediate => RmImm;
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeCcmpImm(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeCcmpImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
|
public OpCodeCcmpImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
|
||||||
}
|
}
|
||||||
}
|
}
|
|
@ -8,6 +8,8 @@ namespace ARMeilleure.Decoders
|
||||||
|
|
||||||
public ShiftType ShiftType => ShiftType.Lsl;
|
public ShiftType ShiftType => ShiftType.Lsl;
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeCcmpReg(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeCcmpReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
|
public OpCodeCcmpReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
|
||||||
}
|
}
|
||||||
}
|
}
|
|
@ -2,9 +2,11 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeCsel : OpCodeAlu, IOpCodeCond
|
class OpCodeCsel : OpCodeAlu, IOpCodeCond
|
||||||
{
|
{
|
||||||
public int Rm { get; private set; }
|
public int Rm { get; }
|
||||||
|
|
||||||
public Condition Cond { get; private set; }
|
public Condition Cond { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeCsel(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeCsel(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeCsel(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,7 +2,9 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeException : OpCode
|
class OpCodeException : OpCode
|
||||||
{
|
{
|
||||||
public int Id { get; private set; }
|
public int Id { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeException(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeException(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeException(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -7,6 +7,8 @@ namespace ARMeilleure.Decoders
|
||||||
public int Size { get; protected set; }
|
public int Size { get; protected set; }
|
||||||
public bool Extend64 { get; protected set; }
|
public bool Extend64 { get; protected set; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMem(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeMem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeMem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
Rt = (opCode >> 0) & 0x1f;
|
Rt = (opCode >> 0) & 0x1f;
|
||||||
|
|
|
@ -2,8 +2,10 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeMemEx : OpCodeMem
|
class OpCodeMemEx : OpCodeMem
|
||||||
{
|
{
|
||||||
public int Rt2 { get; private set; }
|
public int Rt2 { get; }
|
||||||
public int Rs { get; private set; }
|
public int Rs { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemEx(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeMemEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeMemEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -5,7 +5,7 @@ namespace ARMeilleure.Decoders
|
||||||
public long Immediate { get; protected set; }
|
public long Immediate { get; protected set; }
|
||||||
public bool WBack { get; protected set; }
|
public bool WBack { get; protected set; }
|
||||||
public bool PostIdx { get; protected set; }
|
public bool PostIdx { get; protected set; }
|
||||||
protected bool Unscaled { get; private set; }
|
protected bool Unscaled { get; }
|
||||||
|
|
||||||
private enum MemOp
|
private enum MemOp
|
||||||
{
|
{
|
||||||
|
@ -16,6 +16,8 @@ namespace ARMeilleure.Decoders
|
||||||
Unsigned
|
Unsigned
|
||||||
}
|
}
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemImm(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeMemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeMemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
Extend64 = ((opCode >> 22) & 3) == 2;
|
Extend64 = ((opCode >> 22) & 3) == 2;
|
||||||
|
|
|
@ -2,11 +2,13 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeMemLit : OpCode, IOpCodeLit
|
class OpCodeMemLit : OpCode, IOpCodeLit
|
||||||
{
|
{
|
||||||
public int Rt { get; private set; }
|
public int Rt { get; }
|
||||||
public long Immediate { get; private set; }
|
public long Immediate { get; }
|
||||||
public int Size { get; private set; }
|
public int Size { get; }
|
||||||
public bool Signed { get; private set; }
|
public bool Signed { get; }
|
||||||
public bool Prefetch { get; private set; }
|
public bool Prefetch { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemLit(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeMemLit(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeMemLit(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,7 +2,9 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeMemPair : OpCodeMemImm
|
class OpCodeMemPair : OpCodeMemImm
|
||||||
{
|
{
|
||||||
public int Rt2 { get; private set; }
|
public int Rt2 { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemPair(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeMemPair(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeMemPair(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,10 +2,12 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeMemReg : OpCodeMem
|
class OpCodeMemReg : OpCodeMem
|
||||||
{
|
{
|
||||||
public bool Shift { get; private set; }
|
public bool Shift { get; }
|
||||||
public int Rm { get; private set; }
|
public int Rm { get; }
|
||||||
|
|
||||||
public IntType IntType { get; private set; }
|
public IntType IntType { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemReg(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeMemReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeMemReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,11 +2,13 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeMov : OpCode
|
class OpCodeMov : OpCode
|
||||||
{
|
{
|
||||||
public int Rd { get; private set; }
|
public int Rd { get; }
|
||||||
|
|
||||||
public long Immediate { get; private set; }
|
public long Immediate { get; }
|
||||||
|
|
||||||
public int Bit { get; private set; }
|
public int Bit { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMov(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeMov(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeMov(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,8 +2,10 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeMul : OpCodeAlu
|
class OpCodeMul : OpCodeAlu
|
||||||
{
|
{
|
||||||
public int Rm { get; private set; }
|
public int Rm { get; }
|
||||||
public int Ra { get; private set; }
|
public int Ra { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMul(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeMul(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeMul(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,11 +2,13 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeSimd : OpCode, IOpCodeSimd
|
class OpCodeSimd : OpCode, IOpCodeSimd
|
||||||
{
|
{
|
||||||
public int Rd { get; private set; }
|
public int Rd { get; }
|
||||||
public int Rn { get; private set; }
|
public int Rn { get; }
|
||||||
public int Opc { get; private set; }
|
public int Opc { get; }
|
||||||
public int Size { get; protected set; }
|
public int Size { get; protected set; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimd(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeSimd(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeSimd(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
Rd = (opCode >> 0) & 0x1f;
|
Rd = (opCode >> 0) & 0x1f;
|
||||||
|
|
|
@ -2,7 +2,9 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeSimdCvt : OpCodeSimd
|
class OpCodeSimdCvt : OpCodeSimd
|
||||||
{
|
{
|
||||||
public int FBits { get; private set; }
|
public int FBits { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdCvt(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeSimdCvt(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeSimdCvt(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,7 +2,9 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeSimdExt : OpCodeSimdReg
|
class OpCodeSimdExt : OpCodeSimdReg
|
||||||
{
|
{
|
||||||
public int Imm4 { get; private set; }
|
public int Imm4 { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdExt(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeSimdExt(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeSimdExt(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,9 +2,11 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeSimdFcond : OpCodeSimdReg, IOpCodeCond
|
class OpCodeSimdFcond : OpCodeSimdReg, IOpCodeCond
|
||||||
{
|
{
|
||||||
public int Nzcv { get; private set; }
|
public int Nzcv { get; }
|
||||||
|
|
||||||
public Condition Cond { get; private set; }
|
public Condition Cond { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdFcond(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeSimdFcond(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeSimdFcond(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,9 +2,11 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeSimdFmov : OpCode, IOpCodeSimd
|
class OpCodeSimdFmov : OpCode, IOpCodeSimd
|
||||||
{
|
{
|
||||||
public int Rd { get; private set; }
|
public int Rd { get; }
|
||||||
public long Immediate { get; private set; }
|
public long Immediate { get; }
|
||||||
public int Size { get; private set; }
|
public int Size { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdFmov(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeSimdFmov(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeSimdFmov(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,9 +2,11 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeSimdImm : OpCode, IOpCodeSimd
|
class OpCodeSimdImm : OpCode, IOpCodeSimd
|
||||||
{
|
{
|
||||||
public int Rd { get; private set; }
|
public int Rd { get; }
|
||||||
public long Immediate { get; private set; }
|
public long Immediate { get; }
|
||||||
public int Size { get; private set; }
|
public int Size { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdImm(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeSimdImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeSimdImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,8 +2,10 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeSimdIns : OpCodeSimd
|
class OpCodeSimdIns : OpCodeSimd
|
||||||
{
|
{
|
||||||
public int SrcIndex { get; private set; }
|
public int SrcIndex { get; }
|
||||||
public int DstIndex { get; private set; }
|
public int DstIndex { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdIns(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeSimdIns(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeSimdIns(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,6 +2,8 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeSimdMemImm : OpCodeMemImm, IOpCodeSimd
|
class OpCodeSimdMemImm : OpCodeMemImm, IOpCodeSimd
|
||||||
{
|
{
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemImm(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeSimdMemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeSimdMemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
Size |= (opCode >> 21) & 4;
|
Size |= (opCode >> 21) & 4;
|
||||||
|
|
|
@ -2,12 +2,14 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeSimdMemLit : OpCode, IOpCodeSimd, IOpCodeLit
|
class OpCodeSimdMemLit : OpCode, IOpCodeSimd, IOpCodeLit
|
||||||
{
|
{
|
||||||
public int Rt { get; private set; }
|
public int Rt { get; }
|
||||||
public long Immediate { get; private set; }
|
public long Immediate { get; }
|
||||||
public int Size { get; private set; }
|
public int Size { get; }
|
||||||
public bool Signed => false;
|
public bool Signed => false;
|
||||||
public bool Prefetch => false;
|
public bool Prefetch => false;
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemLit(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeSimdMemLit(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeSimdMemLit(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
int opc = (opCode >> 30) & 3;
|
int opc = (opCode >> 30) & 3;
|
||||||
|
|
|
@ -2,10 +2,12 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeSimdMemMs : OpCodeMemReg, IOpCodeSimd
|
class OpCodeSimdMemMs : OpCodeMemReg, IOpCodeSimd
|
||||||
{
|
{
|
||||||
public int Reps { get; private set; }
|
public int Reps { get; }
|
||||||
public int SElems { get; private set; }
|
public int SElems { get; }
|
||||||
public int Elems { get; private set; }
|
public int Elems { get; }
|
||||||
public bool WBack { get; private set; }
|
public bool WBack { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemMs(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeSimdMemMs(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeSimdMemMs(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,6 +2,8 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeSimdMemPair : OpCodeMemPair, IOpCodeSimd
|
class OpCodeSimdMemPair : OpCodeMemPair, IOpCodeSimd
|
||||||
{
|
{
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemPair(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeSimdMemPair(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeSimdMemPair(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
Size = ((opCode >> 30) & 3) + 2;
|
Size = ((opCode >> 30) & 3) + 2;
|
||||||
|
|
|
@ -2,6 +2,8 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeSimdMemReg : OpCodeMemReg, IOpCodeSimd
|
class OpCodeSimdMemReg : OpCodeMemReg, IOpCodeSimd
|
||||||
{
|
{
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemReg(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeSimdMemReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeSimdMemReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
Size |= (opCode >> 21) & 4;
|
Size |= (opCode >> 21) & 4;
|
||||||
|
|
|
@ -2,10 +2,12 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeSimdMemSs : OpCodeMemReg, IOpCodeSimd
|
class OpCodeSimdMemSs : OpCodeMemReg, IOpCodeSimd
|
||||||
{
|
{
|
||||||
public int SElems { get; private set; }
|
public int SElems { get; }
|
||||||
public int Index { get; private set; }
|
public int Index { get; }
|
||||||
public bool Replicate { get; private set; }
|
public bool Replicate { get; }
|
||||||
public bool WBack { get; private set; }
|
public bool WBack { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemSs(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeSimdMemSs(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeSimdMemSs(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
|
|
@ -2,10 +2,12 @@ namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeSimdReg : OpCodeSimd
|
class OpCodeSimdReg : OpCodeSimd
|
||||||
{
|
{
|
||||||
public bool Bit3 { get; private set; }
|
public bool Bit3 { get; }
|
||||||
public int Ra { get; private set; }
|
public int Ra { get; }
|
||||||
public int Rm { get; protected set; }
|
public int Rm { get; protected set; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdReg(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeSimdReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeSimdReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
Bit3 = ((opCode >> 3) & 0x1) != 0;
|
Bit3 = ((opCode >> 3) & 0x1) != 0;
|
||||||
|
|
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue