fix notNarrow VectorExtract, and add a tiny test to be sure that EmitSaturatingOp with notNarrow flag doesn't send errors
This commit is contained in:
parent
29298192ec
commit
74f52b34a1
3 changed files with 19 additions and 3 deletions
|
@ -884,7 +884,9 @@ namespace ChocolArm64.Instruction
|
||||||
|
|
||||||
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
|
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
|
||||||
|
|
||||||
int Elems = !Scalar ? 8 >> Op.Size : 1;
|
int Bytes = Op.GetBitsCount() >> 3;
|
||||||
|
|
||||||
|
int Elems = !Scalar ? (Narrow ? 8 : Bytes) >> Op.Size : 1;
|
||||||
|
|
||||||
int ESize = 8 << Op.Size;
|
int ESize = 8 << Op.Size;
|
||||||
|
|
||||||
|
@ -912,11 +914,11 @@ namespace ChocolArm64.Instruction
|
||||||
AILLabel LblLe = new AILLabel();
|
AILLabel LblLe = new AILLabel();
|
||||||
AILLabel LblGeEnd = new AILLabel();
|
AILLabel LblGeEnd = new AILLabel();
|
||||||
|
|
||||||
EmitVectorExtract(Context, Op.Rn, Index, Op.Size + 1, SignedSrc);
|
EmitVectorExtract(Context, Op.Rn, Index, Narrow ? Op.Size + 1 : Op.Size, SignedSrc);
|
||||||
|
|
||||||
if (Binary)
|
if (Binary)
|
||||||
{
|
{
|
||||||
EmitVectorExtract(Context, ((AOpCodeSimdReg)Op).Rm, Index, Op.Size + 1, SignedSrc);
|
EmitVectorExtract(Context, ((AOpCodeSimdReg)Op).Rm, Index, Narrow ? Op.Size + 1 : Op.Size, SignedSrc);
|
||||||
}
|
}
|
||||||
|
|
||||||
Emit();
|
Emit();
|
||||||
|
|
|
@ -1126,6 +1126,19 @@ namespace Ryujinx.Tests.Cpu
|
||||||
});
|
});
|
||||||
}
|
}
|
||||||
|
|
||||||
|
[TestCase(0x00000001u, 0x7FFFFFFFu, 0x7FFFFFFFu, true)]
|
||||||
|
public void Sqadd_S(uint A, uint B, uint Result, bool Fpsr)
|
||||||
|
{
|
||||||
|
Vector128<float> V1 = MakeVectorE0(A);
|
||||||
|
Vector128<float> V2 = MakeVectorE0(B);
|
||||||
|
AThreadState ThreadState = SingleOpcode(0x5EA20C20, V1: V1, V2: V2);
|
||||||
|
Assert.Multiple(() =>
|
||||||
|
{
|
||||||
|
Assert.AreEqual(Result, GetVectorE0(ThreadState.V0));
|
||||||
|
Assert.AreEqual(((ThreadState.Fpsr >> 27) & 1) == 1, Fpsr);
|
||||||
|
});
|
||||||
|
}
|
||||||
|
|
||||||
[Test, Description("SQXTN <Vb><d>, <Va><n>")]
|
[Test, Description("SQXTN <Vb><d>, <Va><n>")]
|
||||||
public void Sqxtn_S_HB_SH_DS([Values(0u)] uint Rd,
|
public void Sqxtn_S_HB_SH_DS([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
|
|
|
@ -9,6 +9,7 @@ namespace Ryujinx.Tests.Cpu
|
||||||
{
|
{
|
||||||
public class CpuTestSimdArithmetic : CpuTest
|
public class CpuTestSimdArithmetic : CpuTest
|
||||||
{
|
{
|
||||||
|
|
||||||
[TestCase(0x1E224820u, 0x0000000000000000ul, 0x0000000080000000ul, 0x0000000000000000ul)]
|
[TestCase(0x1E224820u, 0x0000000000000000ul, 0x0000000080000000ul, 0x0000000000000000ul)]
|
||||||
[TestCase(0x1E224820u, 0x0000000080000000ul, 0x0000000000000000ul, 0x0000000000000000ul)]
|
[TestCase(0x1E224820u, 0x0000000080000000ul, 0x0000000000000000ul, 0x0000000000000000ul)]
|
||||||
[TestCase(0x1E224820u, 0x0000000080000000ul, 0x0000000080000000ul, 0x0000000080000000ul)]
|
[TestCase(0x1E224820u, 0x0000000080000000ul, 0x0000000080000000ul, 0x0000000080000000ul)]
|
||||||
|
|
Loading…
Reference in a new issue