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Implement VMOVL and VORR.I32 AArch32 SIMD instructions (#960)
* Implement VMOVL and VORR.I32 AArch32 SIMD instructions * Rename <dt> to <size> on test description * Rename Widen to Long and improve VMOVL implementation a bit
This commit is contained in:
parent
08c0e3829b
commit
89ccec197e
9 changed files with 165 additions and 7 deletions
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@ -1,11 +1,9 @@
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namespace ARMeilleure.Decoders
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namespace ARMeilleure.Decoders
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{
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{
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class OpCode32SimdImm : OpCode32, IOpCode32SimdImm
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class OpCode32SimdImm : OpCode32SimdBase, IOpCode32SimdImm
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{
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{
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public int Vd { get; private set; }
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public bool Q { get; private set; }
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public bool Q { get; private set; }
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public long Immediate { get; private set; }
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public long Immediate { get; private set; }
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public int Size { get; private set; }
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public int Elems => GetBytesCount() >> Size;
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public int Elems => GetBytesCount() >> Size;
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public OpCode32SimdImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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public OpCode32SimdImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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@ -24,7 +22,7 @@
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imm |= ((uint)opCode >> 12) & 0x70;
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imm |= ((uint)opCode >> 12) & 0x70;
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imm |= ((uint)opCode >> 17) & 0x80;
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imm |= ((uint)opCode >> 17) & 0x80;
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(Immediate, Size) = OpCodeSimdHelper.GetSimdImmediateAndSize(cMode, op, imm, fpBaseSize: 2);
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(Immediate, Size) = OpCodeSimdHelper.GetSimdImmediateAndSize(cMode, op, imm);
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RegisterSize = Q ? RegisterSize.Simd128 : RegisterSize.Simd64;
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RegisterSize = Q ? RegisterSize.Simd128 : RegisterSize.Simd64;
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27
ARMeilleure/Decoders/OpCode32SimdLong.cs
Normal file
27
ARMeilleure/Decoders/OpCode32SimdLong.cs
Normal file
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@ -0,0 +1,27 @@
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namespace ARMeilleure.Decoders
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{
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class OpCode32SimdLong : OpCode32SimdBase
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{
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public bool U { get; private set; }
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public OpCode32SimdLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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int imm3h = (opCode >> 19) & 0x7;
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// The value must be a power of 2, otherwise it is the encoding of another instruction.
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switch (imm3h)
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{
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case 1: Size = 0; break;
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case 2: Size = 1; break;
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case 4: Size = 2; break;
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}
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U = ((opCode >> 24) & 0x1) != 0;
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RegisterSize = RegisterSize.Simd64;
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Vd = ((opCode >> 18) & 0x10) | ((opCode >> 12) & 0xf);
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Vm = ((opCode >> 1) & 0x10) | ((opCode >> 0) & 0xf);
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}
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}
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}
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@ -2,7 +2,7 @@
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{
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{
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public static class OpCodeSimdHelper
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public static class OpCodeSimdHelper
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{
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{
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public static (long Immediate, int Size) GetSimdImmediateAndSize(int cMode, int op, long imm, int fpBaseSize = 0)
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public static (long Immediate, int Size) GetSimdImmediateAndSize(int cMode, int op, long imm)
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{
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{
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int modeLow = cMode & 1;
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int modeLow = cMode & 1;
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int modeHigh = cMode >> 1;
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int modeHigh = cMode >> 1;
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@ -158,7 +158,7 @@ namespace ARMeilleure.Decoders
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SetA64("x0011010110xxxxx000011xxxxxxxxxx", InstName.Sdiv, InstEmit.Sdiv, typeof(OpCodeAluBinary));
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SetA64("x0011010110xxxxx000011xxxxxxxxxx", InstName.Sdiv, InstEmit.Sdiv, typeof(OpCodeAluBinary));
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SetA64("10011011001xxxxx0xxxxxxxxxxxxxxx", InstName.Smaddl, InstEmit.Smaddl, typeof(OpCodeMul));
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SetA64("10011011001xxxxx0xxxxxxxxxxxxxxx", InstName.Smaddl, InstEmit.Smaddl, typeof(OpCodeMul));
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SetA64("10011011001xxxxx1xxxxxxxxxxxxxxx", InstName.Smsubl, InstEmit.Smsubl, typeof(OpCodeMul));
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SetA64("10011011001xxxxx1xxxxxxxxxxxxxxx", InstName.Smsubl, InstEmit.Smsubl, typeof(OpCodeMul));
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SetA64("10011011010xxxxx0xxxxxxxxxxxxxxx", InstName.Smul__, InstEmit.Smulh, typeof(OpCodeMul));
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SetA64("10011011010xxxxx0xxxxxxxxxxxxxxx", InstName.Smulh, InstEmit.Smulh, typeof(OpCodeMul));
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SetA64("xx001000100xxxxx1xxxxxxxxxxxxxxx", InstName.Stlr, InstEmit.Stlr, typeof(OpCodeMemEx));
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SetA64("xx001000100xxxxx1xxxxxxxxxxxxxxx", InstName.Stlr, InstEmit.Stlr, typeof(OpCodeMemEx));
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SetA64("1x001000001xxxxx1xxxxxxxxxxxxxxx", InstName.Stlxp, InstEmit.Stlxp, typeof(OpCodeMemEx));
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SetA64("1x001000001xxxxx1xxxxxxxxxxxxxxx", InstName.Stlxp, InstEmit.Stlxp, typeof(OpCodeMemEx));
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SetA64("xx001000000xxxxx1xxxxxxxxxxxxxxx", InstName.Stlxr, InstEmit.Stlxr, typeof(OpCodeMemEx));
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SetA64("xx001000000xxxxx1xxxxxxxxxxxxxxx", InstName.Stlxr, InstEmit.Stlxr, typeof(OpCodeMemEx));
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@ -829,6 +829,9 @@ namespace ARMeilleure.Decoders
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SetA32("1111001x1x000xxxxxxx11xx0x01xxxx", InstName.Vmov, InstEmit32.Vmov_I, typeof(OpCode32SimdImm)); // D/Q (dt - from cmode).
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SetA32("1111001x1x000xxxxxxx11xx0x01xxxx", InstName.Vmov, InstEmit32.Vmov_I, typeof(OpCode32SimdImm)); // D/Q (dt - from cmode).
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SetA32("1111001x1x000xxxxxxx11100x11xxxx", InstName.Vmov, InstEmit32.Vmov_I, typeof(OpCode32SimdImm)); // D/Q I64.
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SetA32("1111001x1x000xxxxxxx11100x11xxxx", InstName.Vmov, InstEmit32.Vmov_I, typeof(OpCode32SimdImm)); // D/Q I64.
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SetA32("<<<<11101x110000xxxx101x01x0xxxx", InstName.Vmov, InstEmit32.Vmov_S, typeof(OpCode32SimdS));
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SetA32("<<<<11101x110000xxxx101x01x0xxxx", InstName.Vmov, InstEmit32.Vmov_S, typeof(OpCode32SimdS));
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SetA32("1111001x1x001000xxx0101000x1xxxx", InstName.Vmovl, InstEmit32.Vmovl, typeof(OpCode32SimdLong));
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SetA32("1111001x1x010000xxx0101000x1xxxx", InstName.Vmovl, InstEmit32.Vmovl, typeof(OpCode32SimdLong));
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SetA32("1111001x1x100000xxx0101000x1xxxx", InstName.Vmovl, InstEmit32.Vmovl, typeof(OpCode32SimdLong));
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SetA32("111100111x11xx10xxxx001000x0xxx0", InstName.Vmovn, InstEmit32.Vmovn, typeof(OpCode32SimdCmpZ));
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SetA32("111100111x11xx10xxxx001000x0xxx0", InstName.Vmovn, InstEmit32.Vmovn, typeof(OpCode32SimdCmpZ));
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SetA32("<<<<11101111xxxxxxxx101000010000", InstName.Vmrs, InstEmit32.Vmrs, typeof(OpCode32SimdSpecial));
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SetA32("<<<<11101111xxxxxxxx101000010000", InstName.Vmrs, InstEmit32.Vmrs, typeof(OpCode32SimdSpecial));
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SetA32("<<<<11101110xxxxxxxx101000010000", InstName.Vmsr, InstEmit32.Vmsr, typeof(OpCode32SimdSpecial));
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SetA32("<<<<11101110xxxxxxxx101000010000", InstName.Vmsr, InstEmit32.Vmsr, typeof(OpCode32SimdSpecial));
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@ -845,6 +848,7 @@ namespace ARMeilleure.Decoders
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SetA32("<<<<11100x01xxxxxxxx101xx0x0xxxx", InstName.Vnmls, InstEmit32.Vnmls_S, typeof(OpCode32SimdRegS));
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SetA32("<<<<11100x01xxxxxxxx101xx0x0xxxx", InstName.Vnmls, InstEmit32.Vnmls_S, typeof(OpCode32SimdRegS));
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SetA32("<<<<11100x10xxxxxxxx101xx1x0xxxx", InstName.Vnmul, InstEmit32.Vnmul_S, typeof(OpCode32SimdRegS));
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SetA32("<<<<11100x10xxxxxxxx101xx1x0xxxx", InstName.Vnmul, InstEmit32.Vnmul_S, typeof(OpCode32SimdRegS));
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SetA32("111100100x10xxxxxxxx0001xxx1xxxx", InstName.Vorr, InstEmit32.Vorr_I, typeof(OpCode32SimdBinary));
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SetA32("111100100x10xxxxxxxx0001xxx1xxxx", InstName.Vorr, InstEmit32.Vorr_I, typeof(OpCode32SimdBinary));
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SetA32("1111001x1x000xxxxxxx0xx10x01xxxx", InstName.Vorr, InstEmit32.Vorr_II, typeof(OpCode32SimdImm));
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SetA32("111100100x<<xxxxxxxx1011x0x1xxxx", InstName.Vpadd, InstEmit32.Vpadd_I, typeof(OpCode32SimdReg));
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SetA32("111100100x<<xxxxxxxx1011x0x1xxxx", InstName.Vpadd, InstEmit32.Vpadd_I, typeof(OpCode32SimdReg));
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SetA32("111100110x00xxxxxxxx1101x0x0xxxx", InstName.Vpadd, InstEmit32.Vpadd_V, typeof(OpCode32SimdReg));
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SetA32("111100110x00xxxxxxxx1101x0x0xxxx", InstName.Vpadd, InstEmit32.Vpadd_V, typeof(OpCode32SimdReg));
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SetA32("111100111x111011xxxx010x0xx0xxxx", InstName.Vrecpe, InstEmit32.Vrecpe, typeof(OpCode32SimdSqrte));
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SetA32("111100111x111011xxxx010x0xx0xxxx", InstName.Vrecpe, InstEmit32.Vrecpe, typeof(OpCode32SimdSqrte));
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.Translation;
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using ARMeilleure.Translation;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.Instructions.InstEmitSimdHelper;
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using static ARMeilleure.Instructions.InstEmitSimdHelper32;
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using static ARMeilleure.Instructions.InstEmitSimdHelper32;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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namespace ARMeilleure.Instructions
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namespace ARMeilleure.Instructions
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{
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{
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}
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}
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}
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}
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public static void Vorr_II(ArmEmitterContext context)
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{
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OpCode32SimdImm op = (OpCode32SimdImm)context.CurrOp;
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long immediate = op.Immediate;
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// Replicate fields to fill the 64-bits, if size is < 64-bits.
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switch (op.Size)
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{
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case 0: immediate *= 0x0101010101010101L; break;
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case 1: immediate *= 0x0001000100010001L; break;
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case 2: immediate *= 0x0000000100000001L; break;
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}
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Operand imm = Const(immediate);
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Operand res = GetVecA32(op.Qd);
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if (op.Q)
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{
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for (int elem = 0; elem < 2; elem++)
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{
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Operand de = EmitVectorExtractZx(context, op.Qd, elem, 3);
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res = EmitVectorInsert(context, res, context.BitwiseOr(de, imm), elem, 3);
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}
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}
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else
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{
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Operand de = EmitVectorExtractZx(context, op.Qd, op.Vd & 1, 3);
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res = EmitVectorInsert(context, res, context.BitwiseOr(de, imm), op.Vd & 1, 3);
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}
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context.Copy(GetVecA32(op.Qd), res);
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}
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private static void EmitBifBit(ArmEmitterContext context, bool notRm)
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private static void EmitBifBit(ArmEmitterContext context, bool notRm)
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{
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{
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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@ -139,6 +139,36 @@ namespace ARMeilleure.Instructions
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}
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}
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}
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}
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public static void Vmovl(ArmEmitterContext context)
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{
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OpCode32SimdLong op = (OpCode32SimdLong)context.CurrOp;
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Operand res = context.VectorZero();
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int elems = op.GetBytesCount() >> op.Size;
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for (int index = 0; index < elems; index++)
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{
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Operand me = EmitVectorExtract32(context, op.Qm, op.Im + index, op.Size, !op.U);
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if (op.Size == 2)
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{
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if (op.U)
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{
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me = context.ZeroExtend32(OperandType.I64, me);
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}
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else
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{
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me = context.SignExtend32(OperandType.I64, me);
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}
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}
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res = EmitVectorInsert(context, res, me, index, op.Size + 1);
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}
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context.Copy(GetVecA32(op.Qd), res);
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}
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public static void Vtbl(ArmEmitterContext context)
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public static void Vtbl(ArmEmitterContext context)
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{
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{
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OpCode32SimdTbl op = (OpCode32SimdTbl)context.CurrOp;
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OpCode32SimdTbl op = (OpCode32SimdTbl)context.CurrOp;
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@ -81,7 +81,7 @@ namespace ARMeilleure.Instructions
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Sdiv,
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Sdiv,
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Smaddl,
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Smaddl,
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Smsubl,
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Smsubl,
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Smul__,
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Smulh,
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Smull,
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Smull,
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Smulw_,
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Smulw_,
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Ssat,
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Ssat,
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Smlaw_,
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Smlaw_,
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Smmla,
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Smmla,
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Smmls,
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Smmls,
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Smul__,
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Smmul,
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Smmul,
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Stl,
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Stl,
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Stlb,
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Stlb,
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Vmla,
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Vmla,
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Vmls,
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Vmls,
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Vmov,
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Vmov,
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Vmovl,
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Vmovn,
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Vmovn,
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Vmrs,
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Vmrs,
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Vmsr,
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Vmsr,
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@ -56,6 +56,34 @@ namespace Ryujinx.Tests.Cpu
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CompareAgainstUnicorn();
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CompareAgainstUnicorn();
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}
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}
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[Test, Pairwise, Description("VORR.I32 <Vd>, #<imm>")]
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public void Vorr_II([Range(0u, 4u)] uint rd,
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[Random(RndCnt)] ulong z,
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[Random(RndCnt)] byte imm,
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[Values(0u, 1u, 2u, 3u)] uint cMode,
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[Values] bool q)
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{
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uint opcode = 0xf2800110u; // VORR.I32 D0, #0
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if (q)
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{
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opcode |= 1 << 6;
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rd <<= 1;
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}
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opcode |= (uint)(imm & 0xf) << 0;
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opcode |= (uint)(imm & 0x70) << 12;
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opcode |= (uint)(imm & 0x80) << 17;
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opcode |= (cMode & 0x3) << 9;
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opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
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V128 v0 = MakeVectorE0E1(z, z);
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SingleOpcode(opcode, v0: v0);
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CompareAgainstUnicorn();
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}
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#endif
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#endif
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}
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}
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}
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}
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@ -228,6 +228,36 @@ namespace Ryujinx.Tests.Cpu
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CompareAgainstUnicorn();
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CompareAgainstUnicorn();
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}
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}
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[Test, Pairwise, Description("VMOVL.<size> <Qd>, <Dm>")]
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public void Vmovl([Values(0u, 1u, 2u, 3u)] uint vm,
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[Values(0u, 2u, 4u, 6u)] uint vd,
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[Values(1u, 2u, 4u)] uint imm3H,
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[Values] bool u)
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{
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// This is not VMOVL because imm3H = 0, but once
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// we shift in the imm3H value it turns into VMOVL.
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uint opcode = 0xf2800a10u; // VMOV.I16 D0, #0
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opcode |= (vm & 0x10) << 1;
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opcode |= (vm & 0xf);
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opcode |= (vd & 0x10) << 18;
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opcode |= (vd & 0xf) << 12;
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opcode |= (imm3H & 0x7) << 19;
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if (u)
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{
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opcode |= 1 << 24;
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}
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V128 v0 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
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V128 v1 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
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V128 v2 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
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V128 v3 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
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SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, v3: v3);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("VTRN.<size> <Vd>, <Vm>")]
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[Test, Pairwise, Description("VTRN.<size> <Vd>, <Vm>")]
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public void Vtrn([Values(0u, 1u, 2u, 3u)] uint vm,
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public void Vtrn([Values(0u, 1u, 2u, 3u)] uint vm,
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[Values(0u, 1u, 2u, 3u)] uint vd,
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[Values(0u, 1u, 2u, 3u)] uint vd,
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Reference in a new issue