gdkchan
5d698a7d8d
Fix LDXP/LDAXP when Rt == Rn ( #274 )
2018-07-16 15:57:15 -03:00
LDj3SNuD
063fae50fe
Fix EmitHighNarrow(), EmitSaturatingNarrowOp() when Rd == Rn || Rd == Rm (& Part != 0). Optimization of EmitVectorTranspose(), EmitVectorUnzip(), EmitVectorZip() algorithms (reduction of the number of operations and their complexity). Add 12 Tests about Trn1/2, Uzp1/2, Zip1/2 (V) instructions. ( #268 )
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* Update CpuTestSimdArithmetic.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update Instructions.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdHelper.cs
* Update AInstEmitSimdMove.cs
* Delete CpuTestSimdMove.cs
2018-07-15 00:53:26 -03:00
LDj3SNuD
be31f5b46d
Improve CountLeadingZeros() algorithm, nits. ( #219 )
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* Update AInstEmitSimdArithmetic.cs
* Update ASoftFallback.cs
* Update ASoftFallback.cs
* Update ASoftFallback.cs
* Update AInstEmitSimdArithmetic.cs
2018-07-14 15:07:44 -03:00
gdkchan
514218ab98
Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits ( #225 )
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* Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions
* Address PR feedback
* Address PR feedback
* Remove another useless temp var
* nit: Alignment
* Replace Context.CurrOp.GetBitsCount() with Op.GetBitsCount()
* Fix encodings and move flag bit test out of the loop
2018-07-14 13:13:02 -03:00
Merry
b233ae964f
AInstEmitSimdCvt: Half-precision to single-precision conversion ( #235 )
2018-07-12 15:51:02 -03:00
gdkchan
0a36bfbf92
Fix ZIP/UZP/TRN instructions when Rd == Rn || Rd == Rm ( #239 )
2018-07-09 22:48:28 -03:00
Merry
0f8f40486d
ChocolArm64: More accurate implementation of Frecpe & Frecps ( #228 )
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* ChocolArm64: More accurate implementation of Frecpe
* ChocolArm64: Handle infinities and zeros in Frecps
2018-07-08 16:54:47 -03:00
Merry
af1516a146
ASoftFloat: Fix InvSqrtEstimate for negative values ( #233 )
2018-07-08 12:41:46 -03:00
gdkchan
c99b2884e4
Remove broken adds/cmn with condition check optimization ( #218 )
2018-07-03 21:54:05 -03:00
gdkchan
741773910d
Add SMAXP, SMINP, UMAX, UMAXP, UMIN and UMINP cpu instructions ( #200 )
2018-07-03 03:31:48 -03:00
LDj3SNuD
c228cf320d
Add Rbit_V instruction. Add 8 tests (Rbit_V; Rev16_V, Rev32_V, Rev64_V). Improve CountSetBits8() algorithm. ( #212 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdLogical.cs
* Update AVectorHelper.cs
* Update ASoftFallback.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Improve CountSetBits8() algorithm.
* Improve CountSetBits8() algorithm.
2018-07-03 03:31:16 -03:00
LDj3SNuD
53934e8872
Add Saba_V, Sabal_V, Sabd_V, Sabdl_V, Uaba_V, Uabal_V; Update Uabd_V, Uabdl_V. Add 16 tests. ( #204 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdHelper.cs
* Update Instructions.cs
* Update CpuTest.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
2018-06-30 12:40:41 -03:00
gdkchan
4c7c21634e
Add Sse2 fallback to Vector{Extract|Insert}Single methods on the CPU ( #193 )
2018-06-28 20:52:32 -03:00
gdkchan
bc26aa558a
Add support for the FMLA (by element/scalar) instruction ( #187 )
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* Add support for the FMLA (by element/scalar) instruction
* Fix encoding
2018-06-28 20:51:38 -03:00
gdkchan
65105c2a3b
Implement SvcGetThreadContext3
2018-06-26 01:10:15 -03:00
LDj3SNuD
c818093528
Add Sqxtun_S, Sqxtun_V with 3 tests. ( #188 )
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* Update AInstEmitSimdArithmetic.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
2018-06-25 23:36:20 -03:00
LDj3SNuD
8f6387128a
Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. ( #183 )
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* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-25 22:32:29 -03:00
gdkchan
37a6e84fd4
Add REV16/32 (vector) instructions and fix REV64
2018-06-25 18:40:55 -03:00
Rygnus
0bec9d8439
Add opcodes SQXTUN_S and SQXTUN_V ( #184 )
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* Add SQXTUN_S and SQXTUN_V
Part 1/2 of commit
* Add SQXTUN_S and SQXTUN_V (2/2)
Part 2/2 of commit
2018-06-25 14:23:46 -03:00
gdkchan
e7559f128f
Small OpenGL Renderer refactoring ( #177 )
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* Call OpenGL functions directly, remove the pfifo thread, some refactoring
* Fix PerformanceStatistics calculating the wrong host fps, remove wait event on PFIFO as this wasn't exactly was causing the freezes (may replace with an exception later)
* Organized the Gpu folder a bit more, renamed a few things, address PR feedback
* Make PerformanceStatistics thread safe
* Remove unused constant
* Use unlimited update rate for better pref
2018-06-23 21:39:25 -03:00
gdkchan
3e6afeb513
Fix some thread sync issues ( #172 )
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* Fix some thread sync issues
* Remove some debug stuff
* Ensure that writes to the mutex address clears the exclusive monitor
2018-06-21 23:05:42 -03:00
riperiperi
53ebbcfbd9
Rework signed multiplication. Fixed an edge case and passes all tests. ( #174 )
2018-06-20 10:45:20 -03:00
LDj3SNuD
3bdd109f45
Add Cmeq_S, Cmge_S, Cmgt_S, Cmhi_S, Cmhs_S, Cmle_S, Cmlt_S (Reg, Zero) & Cmtst_S compare instructions. Add 22 compare tests (Scalar, Vector). Add Eor_V, Not_V tests. ( #171 )
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* Add files via upload
* Add files via upload
* Delete CpuTestScalar.cs
* Update CpuTestSimdArithmetic.cs
2018-06-18 14:55:26 -03:00
gdkchan
b747b23607
Add the FADDP (scalar) instruction
2018-06-18 00:41:28 -03:00
riperiperi
afa5bf81e3
Faster soft implementation of smulh and umulh ( #134 )
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* Faster soft implementation of smulh and umulh
* smulh: Fixed mul with 0 acting like it had a negative result.
* Use compliment for negative smulh result.
2018-06-13 10:55:45 -03:00
Lordmau5
46dc89f8dd
Implement Fabs_V ( #146 )
2018-06-12 09:29:16 -03:00
gdkchan
4731c7545d
Fix mistake on astc conversion, make some static methods that shouldn't be public private, remove old commmented out code
2018-06-02 11:44:52 -03:00
gdkchan
9670c096e4
Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now)
2018-05-26 17:50:47 -03:00
gdkchan
30829fce52
Fix wrong type on CMTST instruction
2018-05-23 12:57:28 -03:00
gdkchan
e78737089c
Remove some calls generated on the CPU for inexistent intrinsic methods
2018-05-23 00:27:48 -03:00
gdkchan
7ac5f40532
Add scalar variants of FCVTZS/FCVTZU, fix a issue on Ryushader
2018-05-18 14:44:49 -03:00
gdkchan
f9f111bc85
Add intrinsics support ( #121 )
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* Initial intrinsics support
* Update tests to work with the new Vector128 type and intrinsics
* Drop SSE4.1 requirement
* Fix copy-paste mistake
2018-05-11 20:10:27 -03:00
LDj3SNuD
7cda630aba
Add Sqxtn_S, Sqxtn_V, Uqxtn_S, Uqxtn_V instructions and Tests (6). ( #110 )
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* Update ILGeneratorEx.cs
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update CpuTest.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdArithmetic.cs
2018-04-29 20:39:58 -03:00
LDj3SNuD
a5ad1e9a06
Add Cls_V, Clz_V, Orn_V instructions. Add 18 Tests: And_V, Bic_V, Bif_V, Bit_V, Bsl_V, Cls_V, Clz_V, Orn_V, Orr_V. ( #104 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdLogical.cs
* Update AInstEmitSimdArithmetic.cs
* Update ASoftFallback.cs
* Update AInstEmitAlu.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimdReg.cs
* Update CpuTestSimd.cs
2018-04-25 23:20:22 -03:00
gdkchan
a8ba340dde
Improved logging ( #103 )
2018-04-24 15:57:39 -03:00
gdkchan
db0aa54233
Print guest stack trace on a few points that can throw exceptions
2018-04-22 02:48:17 -03:00
gdkchan
bd9b1e2c6b
Stub a few services, add support for generating call stacks on the CPU
2018-04-22 01:22:46 -03:00
LDj3SNuD
2ccd995cb2
Add ADDHN{2}, RADDHN{2}, SUBHN{2}, RSUBHN{2} (vector) instructions. Add 8 Tests. ( #92 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update Bits.cs
* Create CpuTestSimd.cs
* Create CpuTestSimdReg.cs
* Update CpuTestSimd.cs
Provide a better supply of input values for the 20 Simd Tests.
* Update CpuTestSimdReg.cs
Provide a better supply of input values for the 20 Simd Tests.
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
2018-04-20 12:40:15 -03:00
MS-DOS1999
76a5972378
Fix Fmin/max and add vector version, add and modifying fmin/max tests ( #89 )
2018-04-19 00:22:12 -03:00
LDj3SNuD
8b75080639
Add ABS (scalar & vector), ADD (scalar), NEG (scalar) instructions. ( #88 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update AOpCodeTable.cs
2018-04-18 10:56:27 -03:00
LDj3SNuD
262b5b8054
Add TRN1 & TRN2 (vector) instructions. Add 4 simple tests (4S, 8B). ( #77 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdMove.cs
* Update CpuTestSimdMove.cs
* Update AInstEmitSimdMove.cs
* Update CpuTestSimdMove.cs
2018-04-12 11:52:00 -03:00
gdkchan
cb29b4303c
[CPU] Fix CNT instruction
2018-04-10 20:58:32 -03:00
LDj3SNuD
7acd0e0122
Add FMUL (scalar, by element) instruction; add FRECPE, FRECPS (scalar & vector) instructions. Add 5 simple tests. ( #74 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdHelper.cs
* Update CpuTestSimdArithmetic.cs
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
2018-04-08 16:08:57 -03:00
gdkchan
702daf2ff4
[CPU] Fail early when the index/size of the vector is invalid
2018-04-06 15:39:39 -03:00
gdkchan
df3cbadceb
Fix FRSQRTS and FCM* (scalar) instructions
2018-04-06 10:20:17 -03:00
gdkchan
36d9130592
Add FMLS (vector) instruction
2018-04-06 01:41:54 -03:00
gdkchan
f15b1c76a1
Add FRSQRTS and FCM* instructions
2018-04-05 23:28:12 -03:00
Merry
39f20d8d1a
Implement Frsqrte_S ( #72 )
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* Implement Frsqrte_S
* Implement Frsqrte_V
* Add Frsqrte_S test
2018-04-05 20:36:19 -03:00
gdkchan
45c078d782
Add Faddp (vector) instruction
2018-04-04 22:13:10 -03:00
gdkchan
7fe12ad169
Add FNEG (vector) instruction
2018-04-04 16:36:07 -03:00