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106 lines
3.1 KiB
C++
106 lines
3.1 KiB
C++
// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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void IADD(TranslatorVisitor& v, u64 insn, const IR::U32 op_b, bool neg_a, bool po, bool sat, bool x,
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bool cc) {
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union {
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u64 raw;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<8, 8, IR::Reg> src_a;
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} const iadd{insn};
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if (sat) {
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throw NotImplementedException("IADD SAT");
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}
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if (x && po) {
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throw NotImplementedException("IADD X+PO");
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}
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// Operand A is always read from here, negated if needed
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IR::U32 op_a{v.X(iadd.src_a)};
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if (neg_a) {
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op_a = v.ir.INeg(op_a);
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}
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// Add both operands
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IR::U32 result{v.ir.IAdd(op_a, op_b)};
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if (x) {
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const IR::U32 carry{v.ir.Select(v.ir.GetCFlag(), v.ir.Imm32(1), v.ir.Imm32(0))};
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result = v.ir.IAdd(result, carry);
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}
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if (po) {
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// .PO adds one to the result
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result = v.ir.IAdd(result, v.ir.Imm32(1));
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}
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if (cc) {
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// Store flags
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// TODO: Does this grab the result pre-PO or after?
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if (po) {
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throw NotImplementedException("IADD CC+PO");
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}
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// TODO: How does CC behave when X is set?
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if (x) {
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throw NotImplementedException("IADD X+CC");
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}
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v.SetZFlag(v.ir.GetZeroFromOp(result));
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v.SetSFlag(v.ir.GetSignFromOp(result));
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v.SetCFlag(v.ir.GetCarryFromOp(result));
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v.SetOFlag(v.ir.GetOverflowFromOp(result));
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}
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// Store result
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v.X(iadd.dest_reg, result);
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}
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void IADD(TranslatorVisitor& v, u64 insn, IR::U32 op_b) {
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union {
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u64 insn;
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BitField<43, 1, u64> x;
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BitField<47, 1, u64> cc;
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BitField<48, 2, u64> three_for_po;
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BitField<48, 1, u64> neg_b;
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BitField<49, 1, u64> neg_a;
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BitField<50, 1, u64> sat;
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} const iadd{insn};
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const bool po{iadd.three_for_po == 3};
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const bool neg_a{!po && iadd.neg_a != 0};
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if (!po && iadd.neg_b != 0) {
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op_b = v.ir.INeg(op_b);
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}
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IADD(v, insn, op_b, iadd.neg_a != 0, po, iadd.sat != 0, iadd.x != 0, iadd.cc != 0);
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}
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} // Anonymous namespace
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void TranslatorVisitor::IADD_reg(u64 insn) {
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IADD(*this, insn, GetReg20(insn));
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}
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void TranslatorVisitor::IADD_cbuf(u64 insn) {
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IADD(*this, insn, GetCbuf(insn));
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}
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void TranslatorVisitor::IADD_imm(u64 insn) {
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IADD(*this, insn, GetImm20(insn));
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}
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void TranslatorVisitor::IADD32I(u64 insn) {
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union {
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u64 raw;
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BitField<52, 1, u64> cc;
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BitField<53, 1, u64> x;
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BitField<54, 1, u64> sat;
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BitField<55, 2, u64> three_for_po;
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BitField<56, 1, u64> neg_a;
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} const iadd32i{insn};
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const bool po{iadd32i.three_for_po == 3};
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const bool neg_a{!po && iadd32i.neg_a != 0};
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IADD(*this, insn, GetImm32(insn), neg_a, po, iadd32i.sat != 0, iadd32i.x != 0, iadd32i.cc != 0);
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}
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} // namespace Shader::Maxwell
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