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suyu/src/shader_recompiler/backend/spirv/emit_spirv.h

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shader: Add pools and rename files
2021-02-06 03:11:23 +01:00
// Copyright 2021 yuzu Emulator Project
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
#pragma once
spirv: Initial SPIR-V support
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#include <sirit/sirit.h>
#include "common/common_types.h"
spirv: Initial bindings support
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#include "shader_recompiler/backend/spirv/emit_context.h"
shader: Add pools and rename files
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#include "shader_recompiler/frontend/ir/program.h"
shader: Add denorm flush support
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#include "shader_recompiler/profile.h"
shader: Add pools and rename files
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namespace Shader::Backend::SPIRV {
spirv: Remove dependencies on Environment when generating SPIR-V
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[[nodiscard]] std::vector<u32> EmitSPIRV(const Profile& profile, IR::Program& program,
u32& binding);
spirv: Initial SPIR-V support
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shader: Primitive Vulkan integration
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// Microinstruction emitters
Id EmitPhi(EmitContext& ctx, IR::Inst* inst);
void EmitVoid(EmitContext& ctx);
Id EmitIdentity(EmitContext& ctx, const IR::Value& value);
shader: Add partial rasterizer integration
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void EmitBranch(EmitContext& ctx, Id label);
void EmitBranchConditional(EmitContext& ctx, Id condition, Id true_label, Id false_label);
void EmitLoopMerge(EmitContext& ctx, Id merge_label, Id continue_label);
void EmitSelectionMerge(EmitContext& ctx, Id merge_label);
shader: Primitive Vulkan integration
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void EmitReturn(EmitContext& ctx);
shader: Implement BRX
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void EmitUnreachable(EmitContext& ctx);
shader: Add partial rasterizer integration
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void EmitDemoteToHelperInvocation(EmitContext& ctx, Id continue_label);
shader: Implement BAR and fix memory barriers
2021-04-04 08:04:48 +02:00
void EmitBarrier(EmitContext& ctx);
shader: Fix memory barriers
2021-04-17 08:21:03 +02:00
void EmitWorkgroupMemoryBarrier(EmitContext& ctx);
void EmitDeviceMemoryBarrier(EmitContext& ctx);
shader: Implement NDC [-1, 1], attribute types and default varying initialization
2021-03-24 05:33:45 +01:00
void EmitPrologue(EmitContext& ctx);
void EmitEpilogue(EmitContext& ctx);
shader: Implement geometry shaders
2021-04-13 00:41:22 +02:00
void EmitEmitVertex(EmitContext& ctx, const IR::Value& stream);
void EmitEndPrimitive(EmitContext& ctx, const IR::Value& stream);
shader: Primitive Vulkan integration
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void EmitGetRegister(EmitContext& ctx);
void EmitSetRegister(EmitContext& ctx);
void EmitGetPred(EmitContext& ctx);
void EmitSetPred(EmitContext& ctx);
void EmitSetGotoVariable(EmitContext& ctx);
void EmitGetGotoVariable(EmitContext& ctx);
shader: Implement BRX
2021-03-27 22:30:24 +01:00
void EmitSetIndirectBranchVariable(EmitContext& ctx);
void EmitGetIndirectBranchVariable(EmitContext& ctx);
shader: Partial implementation of LDC
2021-03-09 21:14:57 +01:00
Id EmitGetCbufU8(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
Id EmitGetCbufS8(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
Id EmitGetCbufU16(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
Id EmitGetCbufS16(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
Id EmitGetCbufU32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
Id EmitGetCbufF32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
shader: Reimplement GetCbufU64 as GetCbufU32x2 It may generate better code on some compilers and it's easier to handle.
2021-04-04 07:31:09 +02:00
Id EmitGetCbufU32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
shader: Implement geometry shaders
2021-04-13 00:41:22 +02:00
Id EmitGetAttribute(EmitContext& ctx, IR::Attribute attr, Id vertex);
void EmitSetAttribute(EmitContext& ctx, IR::Attribute attr, Id value, Id vertex);
Id EmitGetAttributeIndexed(EmitContext& ctx, Id offset, Id vertex);
void EmitSetAttributeIndexed(EmitContext& ctx, Id offset, Id value, Id vertex);
shader: Implement tessellation shaders, polygon mode and invocation id
2021-04-16 03:46:11 +02:00
Id EmitGetPatch(EmitContext& ctx, IR::Patch patch);
void EmitSetPatch(EmitContext& ctx, IR::Patch patch, Id value);
shader: Add partial rasterizer integration
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void EmitSetFragColor(EmitContext& ctx, u32 index, u32 component, Id value);
shader: Implement SampleMask
2021-04-16 23:47:26 +02:00
void EmitSetSampleMask(EmitContext& ctx, Id value);
shader: Add partial rasterizer integration
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void EmitSetFragDepth(EmitContext& ctx, Id value);
shader: Primitive Vulkan integration
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void EmitGetZFlag(EmitContext& ctx);
void EmitGetSFlag(EmitContext& ctx);
void EmitGetCFlag(EmitContext& ctx);
void EmitGetOFlag(EmitContext& ctx);
void EmitSetZFlag(EmitContext& ctx);
void EmitSetSFlag(EmitContext& ctx);
void EmitSetCFlag(EmitContext& ctx);
void EmitSetOFlag(EmitContext& ctx);
Id EmitWorkgroupId(EmitContext& ctx);
Id EmitLocalInvocationId(EmitContext& ctx);
shader: Implement tessellation shaders, polygon mode and invocation id
2021-04-16 03:46:11 +02:00
Id EmitInvocationId(EmitContext& ctx);
shader: Implement PIXLD.MY_INDEX
2021-04-16 22:22:59 +02:00
Id EmitSampleId(EmitContext& ctx);
shader: Implement SR_THREAD_KILL
2021-04-12 00:16:12 +02:00
Id EmitIsHelperInvocation(EmitContext& ctx);
shader: Implement SR_Y_DIRECTION
2021-04-16 23:52:58 +02:00
Id EmitYDirection(EmitContext& ctx);
shader: Implement LDS, STS, LDL, and STS and use SPIR-V 1.4 when available
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Id EmitLoadLocal(EmitContext& ctx, Id word_offset);
void EmitWriteLocal(EmitContext& ctx, Id word_offset, Id value);
shader: Primitive Vulkan integration
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Id EmitUndefU1(EmitContext& ctx);
Id EmitUndefU8(EmitContext& ctx);
Id EmitUndefU16(EmitContext& ctx);
Id EmitUndefU32(EmitContext& ctx);
Id EmitUndefU64(EmitContext& ctx);
void EmitLoadGlobalU8(EmitContext& ctx);
void EmitLoadGlobalS8(EmitContext& ctx);
void EmitLoadGlobalU16(EmitContext& ctx);
void EmitLoadGlobalS16(EmitContext& ctx);
shader: Add NVN storage buffer fallbacks When we can't track the SSBO origin of a global memory instruction, leave it as a global memory operation and assume these pointers are in the NVN storage buffer slots, then apply a linear search in the shader's runtime.
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Id EmitLoadGlobal32(EmitContext& ctx, Id address);
Id EmitLoadGlobal64(EmitContext& ctx, Id address);
Id EmitLoadGlobal128(EmitContext& ctx, Id address);
shader: Primitive Vulkan integration
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void EmitWriteGlobalU8(EmitContext& ctx);
void EmitWriteGlobalS8(EmitContext& ctx);
void EmitWriteGlobalU16(EmitContext& ctx);
void EmitWriteGlobalS16(EmitContext& ctx);
shader: Add NVN storage buffer fallbacks When we can't track the SSBO origin of a global memory instruction, leave it as a global memory operation and assume these pointers are in the NVN storage buffer slots, then apply a linear search in the shader's runtime.
2021-04-19 21:33:23 +02:00
void EmitWriteGlobal32(EmitContext& ctx, Id address, Id value);
void EmitWriteGlobal64(EmitContext& ctx, Id address, Id value);
void EmitWriteGlobal128(EmitContext& ctx, Id address, Id value);
spirv: Rework storage buffers and shader memory
2021-04-13 10:32:21 +02:00
Id EmitLoadStorageU8(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
Id EmitLoadStorageS8(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
Id EmitLoadStorageU16(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
Id EmitLoadStorageS16(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
shader: Primitive Vulkan integration
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Id EmitLoadStorage32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
spirv: Implement VertexId and InstanceId, refactor code
2021-03-20 23:11:56 +01:00
Id EmitLoadStorage64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
Id EmitLoadStorage128(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
spirv: Rework storage buffers and shader memory
2021-04-13 10:32:21 +02:00
void EmitWriteStorageU8(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
void EmitWriteStorageS8(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
void EmitWriteStorageU16(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
void EmitWriteStorageS16(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
shader: Primitive Vulkan integration
2021-02-17 04:59:28 +01:00
void EmitWriteStorage32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
spirv: Add lower fp16 to fp32 pass
2021-02-19 22:10:18 +01:00
void EmitWriteStorage64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
shader: Initial support for textures and TEX
2021-03-08 22:31:53 +01:00
void EmitWriteStorage128(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
shader: Implement LDS, STS, LDL, and STS and use SPIR-V 1.4 when available
2021-03-29 00:53:34 +02:00
Id EmitLoadSharedU8(EmitContext& ctx, Id offset);
Id EmitLoadSharedS8(EmitContext& ctx, Id offset);
Id EmitLoadSharedU16(EmitContext& ctx, Id offset);
Id EmitLoadSharedS16(EmitContext& ctx, Id offset);
Id EmitLoadSharedU32(EmitContext& ctx, Id offset);
Id EmitLoadSharedU64(EmitContext& ctx, Id offset);
Id EmitLoadSharedU128(EmitContext& ctx, Id offset);
void EmitWriteSharedU8(EmitContext& ctx, Id offset, Id value);
void EmitWriteSharedU16(EmitContext& ctx, Id offset, Id value);
void EmitWriteSharedU32(EmitContext& ctx, Id offset, Id value);
void EmitWriteSharedU64(EmitContext& ctx, Id offset, Id value);
void EmitWriteSharedU128(EmitContext& ctx, Id offset, Id value);
shader: Refactor PTP and other minor changes
2021-03-26 20:46:07 +01:00
Id EmitCompositeConstructU32x2(EmitContext& ctx, Id e1, Id e2);
spirv: Add lower fp16 to fp32 pass
2021-02-19 22:10:18 +01:00
Id EmitCompositeConstructU32x3(EmitContext& ctx, Id e1, Id e2, Id e3);
Id EmitCompositeConstructU32x4(EmitContext& ctx, Id e1, Id e2, Id e3, Id e4);
Id EmitCompositeExtractU32x2(EmitContext& ctx, Id composite, u32 index);
Id EmitCompositeExtractU32x3(EmitContext& ctx, Id composite, u32 index);
Id EmitCompositeExtractU32x4(EmitContext& ctx, Id composite, u32 index);
shader: Implement HADD2
2021-03-03 07:07:19 +01:00
Id EmitCompositeInsertU32x2(EmitContext& ctx, Id composite, Id object, u32 index);
Id EmitCompositeInsertU32x3(EmitContext& ctx, Id composite, Id object, u32 index);
Id EmitCompositeInsertU32x4(EmitContext& ctx, Id composite, Id object, u32 index);
shader: Refactor PTP and other minor changes
2021-03-26 20:46:07 +01:00
Id EmitCompositeConstructF16x2(EmitContext& ctx, Id e1, Id e2);
shader: Implement HADD2
2021-03-03 07:07:19 +01:00
Id EmitCompositeConstructF16x3(EmitContext& ctx, Id e1, Id e2, Id e3);
Id EmitCompositeConstructF16x4(EmitContext& ctx, Id e1, Id e2, Id e3, Id e4);
spirv: Add lower fp16 to fp32 pass
2021-02-19 22:10:18 +01:00
Id EmitCompositeExtractF16x2(EmitContext& ctx, Id composite, u32 index);
Id EmitCompositeExtractF16x3(EmitContext& ctx, Id composite, u32 index);
Id EmitCompositeExtractF16x4(EmitContext& ctx, Id composite, u32 index);
shader: Implement HADD2
2021-03-03 07:07:19 +01:00
Id EmitCompositeInsertF16x2(EmitContext& ctx, Id composite, Id object, u32 index);
Id EmitCompositeInsertF16x3(EmitContext& ctx, Id composite, Id object, u32 index);
Id EmitCompositeInsertF16x4(EmitContext& ctx, Id composite, Id object, u32 index);
shader: Refactor PTP and other minor changes
2021-03-26 20:46:07 +01:00
Id EmitCompositeConstructF32x2(EmitContext& ctx, Id e1, Id e2);
shader: Implement HADD2
2021-03-03 07:07:19 +01:00
Id EmitCompositeConstructF32x3(EmitContext& ctx, Id e1, Id e2, Id e3);
Id EmitCompositeConstructF32x4(EmitContext& ctx, Id e1, Id e2, Id e3, Id e4);
spirv: Add lower fp16 to fp32 pass
2021-02-19 22:10:18 +01:00
Id EmitCompositeExtractF32x2(EmitContext& ctx, Id composite, u32 index);
Id EmitCompositeExtractF32x3(EmitContext& ctx, Id composite, u32 index);
Id EmitCompositeExtractF32x4(EmitContext& ctx, Id composite, u32 index);
shader: Implement HADD2
2021-03-03 07:07:19 +01:00
Id EmitCompositeInsertF32x2(EmitContext& ctx, Id composite, Id object, u32 index);
Id EmitCompositeInsertF32x3(EmitContext& ctx, Id composite, Id object, u32 index);
Id EmitCompositeInsertF32x4(EmitContext& ctx, Id composite, Id object, u32 index);
shader: Primitive Vulkan integration
2021-02-17 04:59:28 +01:00
void EmitCompositeConstructF64x2(EmitContext& ctx);
void EmitCompositeConstructF64x3(EmitContext& ctx);
void EmitCompositeConstructF64x4(EmitContext& ctx);
void EmitCompositeExtractF64x2(EmitContext& ctx);
void EmitCompositeExtractF64x3(EmitContext& ctx);
void EmitCompositeExtractF64x4(EmitContext& ctx);
shader: Implement HADD2
2021-03-03 07:07:19 +01:00
Id EmitCompositeInsertF64x2(EmitContext& ctx, Id composite, Id object, u32 index);
Id EmitCompositeInsertF64x3(EmitContext& ctx, Id composite, Id object, u32 index);
Id EmitCompositeInsertF64x4(EmitContext& ctx, Id composite, Id object, u32 index);
shader: Implement R2P
2021-03-08 04:01:22 +01:00
Id EmitSelectU1(EmitContext& ctx, Id cond, Id true_value, Id false_value);
shader: FMUL, select, RRO, and MUFU fixes
2021-02-23 02:59:16 +01:00
Id EmitSelectU8(EmitContext& ctx, Id cond, Id true_value, Id false_value);
Id EmitSelectU16(EmitContext& ctx, Id cond, Id true_value, Id false_value);
Id EmitSelectU32(EmitContext& ctx, Id cond, Id true_value, Id false_value);
Id EmitSelectU64(EmitContext& ctx, Id cond, Id true_value, Id false_value);
Id EmitSelectF16(EmitContext& ctx, Id cond, Id true_value, Id false_value);
Id EmitSelectF32(EmitContext& ctx, Id cond, Id true_value, Id false_value);
shader: Implement DMNMX, DSET, DSETP
2021-03-22 00:28:37 +01:00
Id EmitSelectF64(EmitContext& ctx, Id cond, Id true_value, Id false_value);
shader: Primitive Vulkan integration
2021-02-17 04:59:28 +01:00
void EmitBitCastU16F16(EmitContext& ctx);
Id EmitBitCastU32F32(EmitContext& ctx, Id value);
void EmitBitCastU64F64(EmitContext& ctx);
void EmitBitCastF16U16(EmitContext& ctx);
Id EmitBitCastF32U32(EmitContext& ctx, Id value);
void EmitBitCastF64U64(EmitContext& ctx);
shader: Implement LEA
2021-03-05 07:15:16 +01:00
Id EmitPackUint2x32(EmitContext& ctx, Id value);
spirv: Add lower fp16 to fp32 pass
2021-02-19 22:10:18 +01:00
Id EmitUnpackUint2x32(EmitContext& ctx, Id value);
Id EmitPackFloat2x16(EmitContext& ctx, Id value);
Id EmitUnpackFloat2x16(EmitContext& ctx, Id value);
Id EmitPackHalf2x16(EmitContext& ctx, Id value);
Id EmitUnpackHalf2x16(EmitContext& ctx, Id value);
Id EmitPackDouble2x32(EmitContext& ctx, Id value);
Id EmitUnpackDouble2x32(EmitContext& ctx, Id value);
shader: Primitive Vulkan integration
2021-02-17 04:59:28 +01:00
void EmitGetZeroFromOp(EmitContext& ctx);
void EmitGetSignFromOp(EmitContext& ctx);
void EmitGetCarryFromOp(EmitContext& ctx);
void EmitGetOverflowFromOp(EmitContext& ctx);
shader: Initial support for textures and TEX
2021-03-08 22:31:53 +01:00
void EmitGetSparseFromOp(EmitContext& ctx);
shader: Implement SHFL
2021-03-25 16:31:37 +01:00
void EmitGetInBoundsFromOp(EmitContext& ctx);
shader: Rename, implement FADD.SAT and P2R (imm)
2021-02-21 21:50:14 +01:00
Id EmitFPAbs16(EmitContext& ctx, Id value);
Id EmitFPAbs32(EmitContext& ctx, Id value);
Id EmitFPAbs64(EmitContext& ctx, Id value);
shader: Primitive Vulkan integration
2021-02-17 04:59:28 +01:00
Id EmitFPAdd16(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
Id EmitFPAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
Id EmitFPAdd64(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
Id EmitFPFma16(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c);
Id EmitFPFma32(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c);
Id EmitFPFma64(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c);
shader: Implement FMNMX And add a const in FCMP
2021-03-14 07:23:56 +01:00
Id EmitFPMax32(EmitContext& ctx, Id a, Id b);
Id EmitFPMax64(EmitContext& ctx, Id a, Id b);
Id EmitFPMin32(EmitContext& ctx, Id a, Id b);
Id EmitFPMin64(EmitContext& ctx, Id a, Id b);
shader: Primitive Vulkan integration
2021-02-17 04:59:28 +01:00
Id EmitFPMul16(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
Id EmitFPMul32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
Id EmitFPMul64(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
shader: Rename, implement FADD.SAT and P2R (imm)
2021-02-21 21:50:14 +01:00
Id EmitFPNeg16(EmitContext& ctx, Id value);
Id EmitFPNeg32(EmitContext& ctx, Id value);
Id EmitFPNeg64(EmitContext& ctx, Id value);
shader: FMUL, select, RRO, and MUFU fixes
2021-02-23 02:59:16 +01:00
Id EmitFPSin(EmitContext& ctx, Id value);
Id EmitFPCos(EmitContext& ctx, Id value);
Id EmitFPExp2(EmitContext& ctx, Id value);
Id EmitFPLog2(EmitContext& ctx, Id value);
Id EmitFPRecip32(EmitContext& ctx, Id value);
Id EmitFPRecip64(EmitContext& ctx, Id value);
Id EmitFPRecipSqrt32(EmitContext& ctx, Id value);
Id EmitFPRecipSqrt64(EmitContext& ctx, Id value);
Id EmitFPSqrt(EmitContext& ctx, Id value);
shader: Rename, implement FADD.SAT and P2R (imm)
2021-02-21 21:50:14 +01:00
Id EmitFPSaturate16(EmitContext& ctx, Id value);
Id EmitFPSaturate32(EmitContext& ctx, Id value);
Id EmitFPSaturate64(EmitContext& ctx, Id value);
shader: Fix F2I
2021-03-24 00:02:30 +01:00
Id EmitFPClamp16(EmitContext& ctx, Id value, Id min_value, Id max_value);
Id EmitFPClamp32(EmitContext& ctx, Id value, Id min_value, Id max_value);
Id EmitFPClamp64(EmitContext& ctx, Id value, Id min_value, Id max_value);
spirv: Add lower fp16 to fp32 pass
2021-02-19 22:10:18 +01:00
Id EmitFPRoundEven16(EmitContext& ctx, Id value);
Id EmitFPRoundEven32(EmitContext& ctx, Id value);
Id EmitFPRoundEven64(EmitContext& ctx, Id value);
Id EmitFPFloor16(EmitContext& ctx, Id value);
Id EmitFPFloor32(EmitContext& ctx, Id value);
Id EmitFPFloor64(EmitContext& ctx, Id value);
Id EmitFPCeil16(EmitContext& ctx, Id value);
Id EmitFPCeil32(EmitContext& ctx, Id value);
Id EmitFPCeil64(EmitContext& ctx, Id value);
Id EmitFPTrunc16(EmitContext& ctx, Id value);
Id EmitFPTrunc32(EmitContext& ctx, Id value);
Id EmitFPTrunc64(EmitContext& ctx, Id value);
shader: FMUL, select, RRO, and MUFU fixes
2021-02-23 02:59:16 +01:00
Id EmitFPOrdEqual16(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdEqual32(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdEqual64(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordEqual16(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordEqual32(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordEqual64(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdNotEqual16(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdNotEqual32(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdNotEqual64(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordNotEqual16(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordNotEqual32(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordNotEqual64(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdLessThan16(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdLessThan32(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdLessThan64(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordLessThan16(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordLessThan32(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordLessThan64(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdGreaterThan16(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdGreaterThan32(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdGreaterThan64(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordGreaterThan16(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordGreaterThan32(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordGreaterThan64(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdLessThanEqual16(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdLessThanEqual32(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdLessThanEqual64(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordLessThanEqual16(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordLessThanEqual32(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordLessThanEqual64(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdGreaterThanEqual16(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdGreaterThanEqual32(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPOrdGreaterThanEqual64(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordGreaterThanEqual16(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordGreaterThanEqual32(EmitContext& ctx, Id lhs, Id rhs);
Id EmitFPUnordGreaterThanEqual64(EmitContext& ctx, Id lhs, Id rhs);
shader: Add support for fp16 comparisons and misc fixes
2021-03-21 04:42:56 +01:00
Id EmitFPIsNan16(EmitContext& ctx, Id value);
shader: Implement FCMP still need to configure some settings for NV denorm flush and intel NaN
2021-03-11 04:42:17 +01:00
Id EmitFPIsNan32(EmitContext& ctx, Id value);
shader: Add support for fp16 comparisons and misc fixes
2021-03-21 04:42:56 +01:00
Id EmitFPIsNan64(EmitContext& ctx, Id value);
shader: Primitive Vulkan integration
2021-02-17 04:59:28 +01:00
Id EmitIAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
shader: Add NVN storage buffer fallbacks When we can't track the SSBO origin of a global memory instruction, leave it as a global memory operation and assume these pointers are in the NVN storage buffer slots, then apply a linear search in the shader's runtime.
2021-04-19 21:33:23 +02:00
Id EmitIAdd64(EmitContext& ctx, Id a, Id b);
shader: Primitive Vulkan integration
2021-02-17 04:59:28 +01:00
Id EmitISub32(EmitContext& ctx, Id a, Id b);
shader: Add NVN storage buffer fallbacks When we can't track the SSBO origin of a global memory instruction, leave it as a global memory operation and assume these pointers are in the NVN storage buffer slots, then apply a linear search in the shader's runtime.
2021-04-19 21:33:23 +02:00
Id EmitISub64(EmitContext& ctx, Id a, Id b);
shader: Primitive Vulkan integration
2021-02-17 04:59:28 +01:00
Id EmitIMul32(EmitContext& ctx, Id a, Id b);
shader: Fix MOV(reg), add SHL variants and emit neg and abs instructions
2021-02-22 06:45:50 +01:00
Id EmitINeg32(EmitContext& ctx, Id value);
shader: Implement LEA
2021-03-05 07:15:16 +01:00
Id EmitINeg64(EmitContext& ctx, Id value);
shader: Fix MOV(reg), add SHL variants and emit neg and abs instructions
2021-02-22 06:45:50 +01:00
Id EmitIAbs32(EmitContext& ctx, Id value);
shader: Implement I2F
2021-03-20 09:04:12 +01:00
Id EmitIAbs64(EmitContext& ctx, Id value);
shader: Primitive Vulkan integration
2021-02-17 04:59:28 +01:00
Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift);
shader: Implement SHF
2021-03-07 20:48:03 +01:00
Id EmitShiftLeftLogical64(EmitContext& ctx, Id base, Id shift);
Id EmitShiftRightLogical32(EmitContext& ctx, Id base, Id shift);
Id EmitShiftRightLogical64(EmitContext& ctx, Id base, Id shift);
Id EmitShiftRightArithmetic32(EmitContext& ctx, Id base, Id shift);
Id EmitShiftRightArithmetic64(EmitContext& ctx, Id base, Id shift);
shader: Implement LOP CC
2021-04-12 00:16:47 +02:00
Id EmitBitwiseAnd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
Id EmitBitwiseOr32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
Id EmitBitwiseXor32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
shader: Implement more of XMAD and FFMA32I and fix XMAD.CBCC
2021-02-23 08:46:39 +01:00
Id EmitBitFieldInsert(EmitContext& ctx, Id base, Id insert, Id offset, Id count);
shader: Implement I2I CC
2021-03-29 03:33:52 +02:00
Id EmitBitFieldSExtract(EmitContext& ctx, IR::Inst* inst, Id base, Id offset, Id count);
shader: Implement R2P
2021-03-08 04:01:22 +01:00
Id EmitBitFieldUExtract(EmitContext& ctx, IR::Inst* inst, Id base, Id offset, Id count);
shader: Implement SHR
2021-02-25 06:46:40 +01:00
Id EmitBitReverse32(EmitContext& ctx, Id value);
shader: Implement POPC
2021-02-27 03:41:46 +01:00
Id EmitBitCount32(EmitContext& ctx, Id value);
shader: Implement FLO
2021-03-01 21:58:16 +01:00
Id EmitBitwiseNot32(EmitContext& ctx, Id value);
Id EmitFindSMsb32(EmitContext& ctx, Id value);
Id EmitFindUMsb32(EmitContext& ctx, Id value);
shader: Implement IMNMX
2021-03-01 05:33:53 +01:00
Id EmitSMin32(EmitContext& ctx, Id a, Id b);
Id EmitUMin32(EmitContext& ctx, Id a, Id b);
Id EmitSMax32(EmitContext& ctx, Id a, Id b);
Id EmitUMax32(EmitContext& ctx, Id a, Id b);
shader: Implement I2I CC
2021-03-29 03:33:52 +02:00
Id EmitSClamp32(EmitContext& ctx, IR::Inst* inst, Id value, Id min, Id max);
Id EmitUClamp32(EmitContext& ctx, IR::Inst* inst, Id value, Id min, Id max);
shader: Primitive Vulkan integration
2021-02-17 04:59:28 +01:00
Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs);
shader: Rename, implement FADD.SAT and P2R (imm)
2021-02-21 21:50:14 +01:00
Id EmitULessThan(EmitContext& ctx, Id lhs, Id rhs);
Id EmitIEqual(EmitContext& ctx, Id lhs, Id rhs);
Id EmitSLessThanEqual(EmitContext& ctx, Id lhs, Id rhs);
Id EmitULessThanEqual(EmitContext& ctx, Id lhs, Id rhs);
shader: Primitive Vulkan integration
2021-02-17 04:59:28 +01:00
Id EmitSGreaterThan(EmitContext& ctx, Id lhs, Id rhs);
shader: Rename, implement FADD.SAT and P2R (imm)
2021-02-21 21:50:14 +01:00
Id EmitUGreaterThan(EmitContext& ctx, Id lhs, Id rhs);
Id EmitINotEqual(EmitContext& ctx, Id lhs, Id rhs);
Id EmitSGreaterThanEqual(EmitContext& ctx, Id lhs, Id rhs);
shader: Primitive Vulkan integration
2021-02-17 04:59:28 +01:00
Id EmitUGreaterThanEqual(EmitContext& ctx, Id lhs, Id rhs);
shader: Implement ATOM/S and RED
2021-04-11 08:07:02 +02:00
Id EmitSharedAtomicIAdd32(EmitContext& ctx, Id pointer_offset, Id value);
Id EmitSharedAtomicSMin32(EmitContext& ctx, Id pointer_offset, Id value);
Id EmitSharedAtomicUMin32(EmitContext& ctx, Id pointer_offset, Id value);
Id EmitSharedAtomicSMax32(EmitContext& ctx, Id pointer_offset, Id value);
Id EmitSharedAtomicUMax32(EmitContext& ctx, Id pointer_offset, Id value);
Id EmitSharedAtomicInc32(EmitContext& ctx, Id pointer_offset, Id value);
Id EmitSharedAtomicDec32(EmitContext& ctx, Id pointer_offset, Id value);
Id EmitSharedAtomicAnd32(EmitContext& ctx, Id pointer_offset, Id value);
Id EmitSharedAtomicOr32(EmitContext& ctx, Id pointer_offset, Id value);
Id EmitSharedAtomicXor32(EmitContext& ctx, Id pointer_offset, Id value);
Id EmitSharedAtomicExchange32(EmitContext& ctx, Id pointer_offset, Id value);
Id EmitSharedAtomicExchange64(EmitContext& ctx, Id pointer_offset, Id value);
Id EmitStorageAtomicIAdd32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
Id EmitStorageAtomicSMin32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
Id EmitStorageAtomicUMin32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
Id EmitStorageAtomicSMax32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
Id EmitStorageAtomicUMax32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
Id EmitStorageAtomicInc32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
Id EmitStorageAtomicDec32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
Id EmitStorageAtomicAnd32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
Id EmitStorageAtomicOr32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
Id EmitStorageAtomicXor32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
Id EmitStorageAtomicExchange32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
Id EmitStorageAtomicIAdd64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
Id EmitStorageAtomicSMin64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
Id EmitStorageAtomicUMin64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
Id EmitStorageAtomicSMax64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
Id EmitStorageAtomicUMax64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
Id EmitStorageAtomicAnd64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
Id EmitStorageAtomicOr64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
Id EmitStorageAtomicXor64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
Id EmitStorageAtomicExchange64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
Id EmitStorageAtomicAddF32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
Id EmitStorageAtomicAddF16x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
Id EmitStorageAtomicAddF32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
Id EmitStorageAtomicMinF16x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
Id EmitStorageAtomicMinF32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
Id EmitStorageAtomicMaxF16x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
Id EmitStorageAtomicMaxF32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
Id value);
Id EmitGlobalAtomicIAdd32(EmitContext& ctx);
Id EmitGlobalAtomicSMin32(EmitContext& ctx);
Id EmitGlobalAtomicUMin32(EmitContext& ctx);
Id EmitGlobalAtomicSMax32(EmitContext& ctx);
Id EmitGlobalAtomicUMax32(EmitContext& ctx);
Id EmitGlobalAtomicInc32(EmitContext& ctx);
Id EmitGlobalAtomicDec32(EmitContext& ctx);
Id EmitGlobalAtomicAnd32(EmitContext& ctx);
Id EmitGlobalAtomicOr32(EmitContext& ctx);
Id EmitGlobalAtomicXor32(EmitContext& ctx);
Id EmitGlobalAtomicExchange32(EmitContext& ctx);
Id EmitGlobalAtomicIAdd64(EmitContext& ctx);
Id EmitGlobalAtomicSMin64(EmitContext& ctx);
Id EmitGlobalAtomicUMin64(EmitContext& ctx);
Id EmitGlobalAtomicSMax64(EmitContext& ctx);
Id EmitGlobalAtomicUMax64(EmitContext& ctx);
Id EmitGlobalAtomicInc64(EmitContext& ctx);
Id EmitGlobalAtomicDec64(EmitContext& ctx);
Id EmitGlobalAtomicAnd64(EmitContext& ctx);
Id EmitGlobalAtomicOr64(EmitContext& ctx);
Id EmitGlobalAtomicXor64(EmitContext& ctx);
Id EmitGlobalAtomicExchange64(EmitContext& ctx);
Id EmitGlobalAtomicAddF32(EmitContext& ctx);
Id EmitGlobalAtomicAddF16x2(EmitContext& ctx);
Id EmitGlobalAtomicAddF32x2(EmitContext& ctx);
Id EmitGlobalAtomicMinF16x2(EmitContext& ctx);
Id EmitGlobalAtomicMinF32x2(EmitContext& ctx);
Id EmitGlobalAtomicMaxF16x2(EmitContext& ctx);
Id EmitGlobalAtomicMaxF32x2(EmitContext& ctx);
spirv: Fixes and Intel specific workarounds
2021-02-22 03:42:38 +01:00
Id EmitLogicalOr(EmitContext& ctx, Id a, Id b);
Id EmitLogicalAnd(EmitContext& ctx, Id a, Id b);
Id EmitLogicalXor(EmitContext& ctx, Id a, Id b);
Id EmitLogicalNot(EmitContext& ctx, Id value);
spirv: Add lower fp16 to fp32 pass
2021-02-19 22:10:18 +01:00
Id EmitConvertS16F16(EmitContext& ctx, Id value);
Id EmitConvertS16F32(EmitContext& ctx, Id value);
Id EmitConvertS16F64(EmitContext& ctx, Id value);
Id EmitConvertS32F16(EmitContext& ctx, Id value);
Id EmitConvertS32F32(EmitContext& ctx, Id value);
Id EmitConvertS32F64(EmitContext& ctx, Id value);
Id EmitConvertS64F16(EmitContext& ctx, Id value);
Id EmitConvertS64F32(EmitContext& ctx, Id value);
Id EmitConvertS64F64(EmitContext& ctx, Id value);
Id EmitConvertU16F16(EmitContext& ctx, Id value);
Id EmitConvertU16F32(EmitContext& ctx, Id value);
Id EmitConvertU16F64(EmitContext& ctx, Id value);
Id EmitConvertU32F16(EmitContext& ctx, Id value);
Id EmitConvertU32F32(EmitContext& ctx, Id value);
Id EmitConvertU32F64(EmitContext& ctx, Id value);
Id EmitConvertU64F16(EmitContext& ctx, Id value);
Id EmitConvertU64F32(EmitContext& ctx, Id value);
Id EmitConvertU64F64(EmitContext& ctx, Id value);
Id EmitConvertU64U32(EmitContext& ctx, Id value);
Id EmitConvertU32U64(EmitContext& ctx, Id value);
shader: Implement HADD2
2021-03-03 07:07:19 +01:00
Id EmitConvertF16F32(EmitContext& ctx, Id value);
Id EmitConvertF32F16(EmitContext& ctx, Id value);
Id EmitConvertF32F64(EmitContext& ctx, Id value);
Id EmitConvertF64F32(EmitContext& ctx, Id value);
shader: Implement I2F
2021-03-20 09:04:12 +01:00
Id EmitConvertF16S8(EmitContext& ctx, Id value);
Id EmitConvertF16S16(EmitContext& ctx, Id value);
shader: Initial support for textures and TEX
2021-03-08 22:31:53 +01:00
Id EmitConvertF16S32(EmitContext& ctx, Id value);
Id EmitConvertF16S64(EmitContext& ctx, Id value);
shader: Implement I2F
2021-03-20 09:04:12 +01:00
Id EmitConvertF16U8(EmitContext& ctx, Id value);
Id EmitConvertF16U16(EmitContext& ctx, Id value);
shader: Initial support for textures and TEX
2021-03-08 22:31:53 +01:00
Id EmitConvertF16U32(EmitContext& ctx, Id value);
Id EmitConvertF16U64(EmitContext& ctx, Id value);
shader: Implement I2F
2021-03-20 09:04:12 +01:00
Id EmitConvertF32S8(EmitContext& ctx, Id value);
Id EmitConvertF32S16(EmitContext& ctx, Id value);
shader: Initial support for textures and TEX
2021-03-08 22:31:53 +01:00
Id EmitConvertF32S32(EmitContext& ctx, Id value);
Id EmitConvertF32S64(EmitContext& ctx, Id value);
shader: Implement I2F
2021-03-20 09:04:12 +01:00
Id EmitConvertF32U8(EmitContext& ctx, Id value);
Id EmitConvertF32U16(EmitContext& ctx, Id value);
shader: Initial support for textures and TEX
2021-03-08 22:31:53 +01:00
Id EmitConvertF32U32(EmitContext& ctx, Id value);
Id EmitConvertF32U64(EmitContext& ctx, Id value);
shader: Implement I2F
2021-03-20 09:04:12 +01:00
Id EmitConvertF64S8(EmitContext& ctx, Id value);
Id EmitConvertF64S16(EmitContext& ctx, Id value);
shader: Initial support for textures and TEX
2021-03-08 22:31:53 +01:00
Id EmitConvertF64S32(EmitContext& ctx, Id value);
Id EmitConvertF64S64(EmitContext& ctx, Id value);
shader: Implement I2F
2021-03-20 09:04:12 +01:00
Id EmitConvertF64U8(EmitContext& ctx, Id value);
Id EmitConvertF64U16(EmitContext& ctx, Id value);
shader: Initial support for textures and TEX
2021-03-08 22:31:53 +01:00
Id EmitConvertF64U32(EmitContext& ctx, Id value);
Id EmitConvertF64U64(EmitContext& ctx, Id value);
Id EmitBindlessImageSampleImplicitLod(EmitContext&);
Id EmitBindlessImageSampleExplicitLod(EmitContext&);
Id EmitBindlessImageSampleDrefImplicitLod(EmitContext&);
Id EmitBindlessImageSampleDrefExplicitLod(EmitContext&);
shader: Implement TLD4 and TLD4_B
2021-03-24 23:41:55 +01:00
Id EmitBindlessImageGather(EmitContext&);
Id EmitBindlessImageGatherDref(EmitContext&);
shader: Add IR opcode for ImageFetch
2021-03-26 19:24:50 +01:00
Id EmitBindlessImageFetch(EmitContext&);
shader: Implement TXQ and fix FragDepth
2021-03-26 22:45:38 +01:00
Id EmitBindlessImageQueryDimensions(EmitContext&);
shader,spirv: Implement ImageQueryLod.
2021-03-28 19:47:52 +02:00
Id EmitBindlessImageQueryLod(EmitContext&);
shader: Implement ImageGradient
2021-03-29 02:00:43 +02:00
Id EmitBindlessImageGradient(EmitContext&);
shader: Implement SULD and SUST
2021-04-09 06:45:39 +02:00
Id EmitBindlessImageRead(EmitContext&);
Id EmitBindlessImageWrite(EmitContext&);
shader: Initial support for textures and TEX
2021-03-08 22:31:53 +01:00
Id EmitBoundImageSampleImplicitLod(EmitContext&);
Id EmitBoundImageSampleExplicitLod(EmitContext&);
Id EmitBoundImageSampleDrefImplicitLod(EmitContext&);
Id EmitBoundImageSampleDrefExplicitLod(EmitContext&);
shader: Implement TLD4 and TLD4_B
2021-03-24 23:41:55 +01:00
Id EmitBoundImageGather(EmitContext&);
Id EmitBoundImageGatherDref(EmitContext&);
shader: Add IR opcode for ImageFetch
2021-03-26 19:24:50 +01:00
Id EmitBoundImageFetch(EmitContext&);
shader: Implement TXQ and fix FragDepth
2021-03-26 22:45:38 +01:00
Id EmitBoundImageQueryDimensions(EmitContext&);
shader,spirv: Implement ImageQueryLod.
2021-03-28 19:47:52 +02:00
Id EmitBoundImageQueryLod(EmitContext&);
shader: Implement ImageGradient
2021-03-29 02:00:43 +02:00
Id EmitBoundImageGradient(EmitContext&);
shader: Implement SULD and SUST
2021-04-09 06:45:39 +02:00
Id EmitBoundImageRead(EmitContext&);
Id EmitBoundImageWrite(EmitContext&);
shader: Initial support for textures and TEX
2021-03-08 22:31:53 +01:00
Id EmitImageSampleImplicitLod(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id coords,
spirv: Use ConstOffset instead of Offset when possible
2021-04-17 07:59:54 +02:00
Id bias_lc, const IR::Value& offset);
shader: Initial support for textures and TEX
2021-03-08 22:31:53 +01:00
Id EmitImageSampleExplicitLod(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id coords,
spirv: Use ConstOffset instead of Offset when possible
2021-04-17 07:59:54 +02:00
Id lod_lc, const IR::Value& offset);
shader: Initial support for textures and TEX
2021-03-08 22:31:53 +01:00
Id EmitImageSampleDrefImplicitLod(EmitContext& ctx, IR::Inst* inst, const IR::Value& index,
spirv: Use ConstOffset instead of Offset when possible
2021-04-17 07:59:54 +02:00
Id coords, Id dref, Id bias_lc, const IR::Value& offset);
shader: Initial support for textures and TEX
2021-03-08 22:31:53 +01:00
Id EmitImageSampleDrefExplicitLod(EmitContext& ctx, IR::Inst* inst, const IR::Value& index,
spirv: Use ConstOffset instead of Offset when possible
2021-04-17 07:59:54 +02:00
Id coords, Id dref, Id lod_lc, const IR::Value& offset);
shader: Refactor PTP and other minor changes
2021-03-26 20:46:07 +01:00
Id EmitImageGather(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id coords,
const IR::Value& offset, const IR::Value& offset2);
shader: Implement TLD4 and TLD4_B
2021-03-24 23:41:55 +01:00
Id EmitImageGatherDref(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id coords,
shader: Refactor PTP and other minor changes
2021-03-26 20:46:07 +01:00
const IR::Value& offset, const IR::Value& offset2, Id dref);
shader: Add IR opcode for ImageFetch
2021-03-26 19:24:50 +01:00
Id EmitImageFetch(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id coords, Id offset,
Id lod, Id ms);
shader: Implement TXQ and fix FragDepth
2021-03-26 22:45:38 +01:00
Id EmitImageQueryDimensions(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id lod);
shader,spirv: Implement ImageQueryLod.
2021-03-28 19:47:52 +02:00
Id EmitImageQueryLod(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id coords);
shader: Implement ImageGradient
2021-03-29 02:00:43 +02:00
Id EmitImageGradient(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id coords,
Id derivates, Id offset, Id lod_clamp);
shader: Implement SULD and SUST
2021-04-09 06:45:39 +02:00
Id EmitImageRead(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id coords);
void EmitImageWrite(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id coords, Id color);
shader: Move LaneId to the warp emission file and fix AMD
2021-04-11 07:22:20 +02:00
Id EmitLaneId(EmitContext& ctx);
shader: Implement VOTE
2021-03-24 01:27:17 +01:00
Id EmitVoteAll(EmitContext& ctx, Id pred);
Id EmitVoteAny(EmitContext& ctx, Id pred);
Id EmitVoteEqual(EmitContext& ctx, Id pred);
Id EmitSubgroupBallot(EmitContext& ctx, Id pred);
shader: Add subgroup masks
2021-04-04 10:17:17 +02:00
Id EmitSubgroupEqMask(EmitContext& ctx);
Id EmitSubgroupLtMask(EmitContext& ctx);
Id EmitSubgroupLeMask(EmitContext& ctx);
Id EmitSubgroupGtMask(EmitContext& ctx);
Id EmitSubgroupGeMask(EmitContext& ctx);
shader: Implement SHFL
2021-03-25 16:31:37 +01:00
Id EmitShuffleIndex(EmitContext& ctx, IR::Inst* inst, Id value, Id index, Id clamp,
Id segmentation_mask);
Id EmitShuffleUp(EmitContext& ctx, IR::Inst* inst, Id value, Id index, Id clamp,
Id segmentation_mask);
Id EmitShuffleDown(EmitContext& ctx, IR::Inst* inst, Id value, Id index, Id clamp,
Id segmentation_mask);
Id EmitShuffleButterfly(EmitContext& ctx, IR::Inst* inst, Id value, Id index, Id clamp,
Id segmentation_mask);
shader: Implement FSWZADD
2021-03-29 04:23:45 +02:00
Id EmitFSwizzleAdd(EmitContext& ctx, Id op_a, Id op_b, Id swizzle);
shader: Add pools and rename files
2021-02-06 03:11:23 +01:00
shader: Implement fine derivates constant propagation
2021-04-17 11:56:45 +02:00
Id EmitDPdxFine(EmitContext& ctx, Id op_a);
Id EmitDPdyFine(EmitContext& ctx, Id op_a);
shader: Add coarse derivatives
2021-04-17 12:51:43 +02:00
Id EmitDPdxCoarse(EmitContext& ctx, Id op_a);
Id EmitDPdyCoarse(EmitContext& ctx, Id op_a);
shader: Add pools and rename files
2021-02-06 03:11:23 +01:00
} // namespace Shader::Backend::SPIRV
Reference in a new issue Copy permalink